Gary A. Van Huben - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 7 from 7

2012

Server-class DDR3 SDRAM memory buffer chipGary A. Van Huben, K. D. Lamb, R. Brett Tremaine, B. E. Aleman, S. M. Rubow, S. H. Rider, Warren E. Maule, Michael E. Wazlowski. ibmrd, 56(1):3, 2012. [doi]

2007

High-speed source-synchronous interface for the IBM System z9 processorDerrin M. Berger, Jonathan Y. Chen, Frank D. Ferraiolo, Jeffrey A. Magee, Gary A. Van Huben. ibmrd, 51(1/2):53-64, 2007. [doi]

Formal Verification of Partial Good Self-Test Fencing StructuresAdrian E. Seigler, Gary A. Van Huben, Hari Mony. FMCAD 2007: 188-191 [doi]

2006

Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal ReasoningTilman Glökler, Jason Baumgartner, Devi Shanmugam, A. E. (Rick) Seigler, Gary A. Van Huben, Barinjato Ramanandray, Hari Mony, Paul Roessler. FMCAD 2006: 3-10 [doi]

2004

Processor subsystem interconnect architecture for a large symmetric multiprocessing systemPak-kin Mak, Gary E. Strait, Michael A. Blake, Kevin W. Kark, Vesselina K. Papazova, A. E. (Rick) Seigler, Gary A. Van Huben, Liyong Wang, George C. Wellwood. ibmrd, 48(3-4):323-338, 2004. [doi]

1999

PLL modeling and verification in a cycle-simulation environmentGary A. Van Huben, Timothy G. McNamara, Thomas E. Gilbert. ibmrd, 43(5):915-926, 1999. [doi]

1997

The role of two-cycle simulation in the S/390 verification processGary A. Van Huben. ibmrd, 41(4&5):593-600, 1997. [doi]

Sign in or sign up to see more results.

runs on WebDSL