Nguyen My Qui - researchr alias

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Viewing Publication 1 - 2 from 2

2020

High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital ConvertersPoki Chen, Jian-Ting Lan, Ruei-Ting Wang, Nguyen My Qui, John Carl Joel S. Marquez, Seiji Kajihara, Yousuke Miyake. tvlsi, 28(4):904-913, 2020. [doi]

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGANguyen My Qui, Chang Hong Lin, Poki Chen. access, 8:172996-173007, 2020. [doi]

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