Takashi Hirayama - researchr alias

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Viewing Publication 1 - 19 from 19

2023

Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic CircuitsTakashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani. ismvl 2023: 153-157 [doi]

Enumerating Empty and Surrounding PolygonsShunta Terui, Katsuhisa Yamanaka, Takashi Hirayama, Takashi Horiyama, Kazuhiro Kurita, Takeaki Uno. ieiceta, 106(9):1082-1091, September 2023. [doi]

2022

A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced SubgraphsTaishu Ito, Yusuke Sano, Katsuhisa Yamanaka, Takashi Hirayama. ieicetd, 105(3):466-473, 2022. [doi]

2020

A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced SubgraphsYusuke Sano, Katsuhisa Yamanaka, Takashi Hirayama. faw 2020: 13-24 [doi]

2019

Exact Exponential Algorithm for Distance-3 Independent Set ProblemKatsuhisa Yamanaka, Shogo Kawaragi, Takashi Hirayama. ieicet, 102-D(3):499-501, 2019. [doi]

2018

Function Design for Minimum Multiple-Control Toffoli Circuits of Reversible Adder/Subtractor Blocks and Arithmetic Logic UnitsMd Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani. ieicet, 101-A(12):2231-2243, 2018. [doi]

2016

New Two-Qubit Gate Library with EntanglementMd Belayet Ali, Takashi Hirayama, Katsuhisa Yamanaka, Yasuaki Nishitani. ismvl 2016: 235-240 [doi]

2014

A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic CircuitsTakashi Hirayama, Hayato Sugawara, Katsuhisa Yamanaka, Yasuaki Nishitani. ieicet, 97-D(9):2253-2261, 2014. [doi]

2011

A Testable Realization for Decimal MultipliersTakashi Hirayama, Yasuaki Nishitani, Seiji Kitamura. ismvl 2011: 248-253 [doi]

2009

Let s make a tennis game!: introduction to game programmingTakashi Hirayama. siggraph 2009: [doi]

Exact Minimization of and-EXOR Expressions of Practical Benchmark FunctionsTakashi Hirayama, Yasuaki Nishitani. jcsc, 18(3):465-486, 2009. [doi]

2006

Efficient Search Methods for Obtaining Exact Minimum AND-EXOR ExpressionsTakashi Hirayama, Yasuaki Nishitani. delta 2006: 137-142 [doi]

Simplification of Exclusive-or Sum-of-Products Expressions Through Function TransformationTakashi Hirayama, M. Takahashi, Yasuaki Nishitani. apccas 2006: 1480-1483 [doi]

2004

New Three-Level Boolean Expression Based on EXOR GatesRyoji Ishikawa, Takashi Hirayama, Goro Koda, Kensuke Shimizu. ieicet, 87-D(5):1214-1222, 2004. [doi]

2002

A faster algorithm of minimizing AND-EXOR expressionsTakashi Hirayama, Yasuaki Nishitani, T. Sato. apccas 2002: 293-298 [doi]

A Faster Algorithm of Minimizing AND-EXOR ExpressionsTakashi Hirayama, Yasuaki Nishitani, Toru Sato. ieiceta, 85-A(12):2708-2714, 2002. [doi]

Pseudocube-based expressions to enhance testabilityR. Ishikawa, T. Igarashi, Takashi Hirayama, K. Shimizu. apccas 2002: 305-310 [doi]

1999

Exor Decomposition with Common Variables and its Application to Multiple-Output NetworksRyoji Ishikawa, Goro Koda, Kensuke Shimizu, Takashi Hirayama. jcsc, 9(1-2):83-97, 1999. [doi]

1996

A simplification algorithm of and-exor expressions guaranteeing minimality for some class of logic functionsTakashi Hirayama, Yasuaki Nishitani. scjapan, 27(3):18-25, 1996. [doi]

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