Takashi Hirayama, Rin Suzuki, Katsuhisa Yamanaka, Yasuaki Nishitani. Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. In 53rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2023, Matsue, Japan, May 22-24, 2023. pages 153-157, IEEE, 2023. [doi]
Abstract is missing.