Yul Chu - researchr alias

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Viewing Publication 1 - 25 from 25

2022

Resource allocation for MEC system with multi-users resource competition based on deep reinforcement learning approachBin Qu, Yan Bai, Yul Chu, Li e Wang, Feng Yu 0006, Xianxian Li. cn, 215:109181, 2022. [doi]

2017

A flexible multi-core functional cache simulator (FM-SIM)Rano Mal, Yul Chu. SCSC 2017: [doi]

2015

Accuracy Enhanced Distributed Sparse Matrix Solver with Block-Based Pivoting for Large Linear SystemsEsteban Torres, Yul Chu, Jin Hwan Park. uic 2015: 758-763 [doi]

2014

Dual-access way-prediction cache for embedded systemsYul Chu, Jin Hwan Park. ejes, 2014:16, 2014. [doi]

2013

A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative CachesYul Chu, Marven Calagos. ijertcs, 4(2):50-61, 2013. [doi]

A Study for a Low-Power Way Predictor for Embedded Data CachesYul Chu. emc 2014: 493-499 [doi]

2012

A parallel simulator for network terminal packet bufferYul Chu, Jin Hwan Park, Yan Bai, Jae Sok-Son, Sanjeev Kumar. simulation, 88(7):884-891, 2012. [doi]

2009

An Efficient Networking Management for a Protocol ProcessorYul Chu, Amit Uppal. icds 2009: 106-111 [doi]

A Dynamic Packet Management in a Protocol ProcessorYul Chu, Amit Uppal, Jae Sok-Son. iccsa 2009: 851-862 [doi]

A Case for a Packet Management in a Network TerminalYul Chu, Yan Bai, Amit Uppal, Jae Sok-Son. NAS 2009: 188-191 [doi]

2007

Packet Buffer Management for a High-Speed Network Interface CardShalini Batra, Yul Chu, Yan Bai. icccn 2007: 191-196 [doi]

Modeling of Trace- and Block-Based CachesAzam Beg, Yul Chu. jcsc, 16(5):711-729, 2007. [doi]

2006

A low-power cache scheme for embedded computingYul Chu, Arul Sandeep Gade, Abhishek Bhaduri. jec, 2(2):261-269, 2006. [doi]

A Case for Dual-Mapping One-Way CachesArul Sandeep Gade, Yul Chu. arcs 2006: 130-144 [doi]

A Shared-Memory Packet Buffer Management in a Network Interface CardAmit Uppal, Yul Chu. apnoms 2006: 517-520 [doi]

2005

2001

An Efficient Indirect Branch PredictorYul Chu, Mabo Robert Ito. europar 2001: 394-402 [doi]

2000

A 2-Way Thrashing-Avoidance Cache (TAC): An Efficient Instruction Cache Scheme for Object-Oriented LanguagesYul Chu, Mabo Robert Ito. iccd 2000: 93-98 [doi]

1996

Parallel SOLVE for direct circuit simulation on a transputer arrayYul Chu, Ausif Mahmood, Donald J. Lynch. hipc 1996: 27-32 [doi]

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