Journal: Computer Architecture Letters

Volume 6, Issue 1

1 -- 4Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero. Explaining Dynamic Cache Partitioning Speed Ups
5 -- 8Natalie D. Enright Jerger, Mikko H. Lipasti, Li-Shiuan Peh. Circuit-Switched Coherence
9 -- 12Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Douglas M. Hawkins, Wei-Chung Hsu, Pen-Chung Yew. CIM: A Reliable Metric for Evaluating Program Phase Classifications
13 -- 16William R. Dieter, A. Kaveti, Henry G. Dietz. Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy
17 -- 20Yoav Etsion, Dror G. Feitelson. Probabilistic Prediction of Temporal Locality
21 -- 24Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser. Nahalal: Cache Organization for Chip Multiprocessors