Journal: Computer Architecture Letters

Volume 6, Issue 2

25 -- 28José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt. Dynamic Predication of Indirect Jumps
29 -- 32Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary. Microarchitectures for Managing Chip Revenues under Process Variations
33 -- 36Jason Zebchuk, Andreas Moshovos. A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
37 -- 40John Kim, James D. Balfour, William J. Dally. Flattened Butterfly Topology for On-Chip Networks
41 -- 44Xiang Xiao, Jaehwan Lee. A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip
45 -- 48David I. August, Jonathan Chang, Sylvain Girbal, Daniel Gracia Pérez, Gilles Mouchard, David A. Penry, Olivier Temam, Neil Vachharajani. UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development
49 -- 52Resit Sendag, Joshua J. Yi, Peng-fei Chuang. Branch Misprediction Prediction: Complementary Branch Predictors
53 -- 56Gulay Yalcin, Oguz Ergin. Using Tag-Match Comparators for Detecting Soft Errors

Volume 6, Issue 1

1 -- 4Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero. Explaining Dynamic Cache Partitioning Speed Ups
5 -- 8Natalie D. Enright Jerger, Mikko H. Lipasti, Li-Shiuan Peh. Circuit-Switched Coherence
9 -- 12Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Douglas M. Hawkins, Wei-Chung Hsu, Pen-Chung Yew. CIM: A Reliable Metric for Evaluating Program Phase Classifications
13 -- 16William R. Dieter, A. Kaveti, Henry G. Dietz. Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy
17 -- 20Yoav Etsion, Dror G. Feitelson. Probabilistic Prediction of Temporal Locality
21 -- 24Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser. Nahalal: Cache Organization for Chip Multiprocessors