| 85 | -- | 89 | Qingchuan Shi, Henry Hoffmann, Omer Khan. A Cross-Layer Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads |
| 90 | -- | 93 | Zhong Zheng, Zhiying Wang, Mikko H. Lipasti. Adaptive Cache and Concurrency Allocation on GPGPUs |
| 94 | -- | 98 | Tony Nowatzki, Venkatraman Govindaraju, Karthikeyan Sankaralingam. A Graph-Based Program Representation for Analyzing Hardware Specialization Approaches |
| 99 | -- | 102 | Seung-Hun Kim, Dohoon Kim, Changmin Lee, Won Seob Jeong, Won Woo Ro, Jean-Luc Gaudiot. A Performance-Energy Model to Evaluate Single Thread Execution Acceleration |
| 103 | -- | 106 | William J. Song, Saibal Mukhopadhyay, Sudhakar Yalamanchili. Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors |
| 107 | -- | 110 | Pavan Poluri, Ahmed Louri. A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems |
| 111 | -- | 114 | Canwen Xiao, Yue Yang, Jianwen Zhu. A Sufficient Condition for Deadlock-Free Adaptive Routing in Mesh Networks |
| 115 | -- | 118 | Sparsh Mittal, Jeffrey S. Vetter. AYUSH: A Technique for Extending Lifetime of SRAM-NVM Hybrid Caches |
| 119 | -- | 122 | Rajit Manohar. Comparing Stochastic and Deterministic Computing |
| 123 | -- | 126 | Bon-Keun Seo, Seungryoul Maeng, Joonwon Lee, Euiseong Seo. DRACO: A Deduplicating FTL for Tangible Extra Capacity |
| 127 | -- | 131 | Vivek Seshadri, Kevin Hsieh, Amirali Boroumand, Donghyuk Lee, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, Todd C. Mowry. Fast Bulk Bitwise AND and OR in DRAM |
| 132 | -- | 135 | Muhammad Shoaib, David A. Wood. LogCA: A Performance Model for Hardware Accelerators |
| 136 | -- | 139 | Dionysios Diamantopoulos, Sotirios Xydis, Kostas Siozios, Dimitrios Soudris. Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures |
| 140 | -- | 143 | Matthew Poremba, Tao Zhang, Yuan Xie 0001. NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems |
| 144 | -- | 147 | Hans Vandierendonck, Ahmad Hassan, Dimitrios S. Nikolopoulos. On the Energy-Efficiency of Byte-Addressable Non-Volatile Memory |
| 148 | -- | 151 | Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar. Resistive Associative Processor |
| 152 | -- | 155 | Suk chan Kang, Chrysostomos Nicopoulos, Ada Gavrilovska, Jongman Kim. Subtleties of Run-Time VirtualAddress Stacks |
| 156 | -- | 159 | Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris. Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS |
| 160 | -- | 163 | Nikola Markovic, Daniel Nemirovsky, Osman S. Ünsal, Mateo Valero, Adrián Cristal. Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core |
| 164 | -- | 168 | Gennady Pekhimenko, Evgeny Bolotin, Mike O'Connor, Onur Mutlu, Todd C. Mowry, Stephen W. Keckler. Toggle-Aware Compression for GPUs |