| 1 | -- | 8 | Basant Kumar Mohanty, Alak Majumdar, Durgesh Nandan, Gyungsu Byun. Guest Editorial: Low Power Computing: Devices, Circuits & Systems for Signal Processing |
| 9 | -- | 29 | Shikha Khurana, Vandana Khanna, Shaveta Arora, Neeraj Kumar Shukla, Mainak Basu. Enhancing Image Security Using Pseudo-Memristive-Based Steganography |
| 30 | -- | 45 | Barnali Chowdhury, Shashank Awasthi, Sanjeev Kumar Metya. Optimized Reversible Full Adder Using Lithium Niobate MZI Based Peres Gate |
| 46 | -- | 73 | K. N. Vijeyakumar, D. Silambarasan, Talluri Vineel Jessy, N. Saravanakumar, M. Manjubala. ASIC Design of Analog Weighted Mean Filter Frontend for Image Processing Application |
| 74 | -- | 115 | Mohammad Faseehuddin, P. Sivagami, Sadia Shireen, Worapong Tangsrirat. Truly Mixed-Mode Universal Filter Capable of Operation in MISO and SIMO Configurations with Quadrature Oscillator as an Application |
| 116 | -- | 130 | Mohamed Mamdouh, Sameh O. Abdellatif. Assessing Cascaded Op-Amp and Pre-Current Amplifier Configurations in Transimpedance Amplifier Interfacing Circuits for Nano-Scale Current-Based Sensor Applications |
| 131 | -- | 152 | Isaac Bruce, Michael Sekyere, Ruohan Yang, Saeid Karimpour, Colin C. McAndrew, Degang Chen 0001. Gradient Minimization in Layout Patterns for Analog Circuits |
| 153 | -- | 172 | Shubhankar Majumdar. Single Transistor Leakage Control for Low Power CMOS Circuits in Bio-implantable RF Receivers |
| 173 | -- | 202 | Zhi-Li Zhang, Siyuan Yao, Puyang Liu, Cheng Li, You Lu, Hailong Wei. An Improved Structure for Reducing Bias Current and Offset Voltage of Operational Amplifier |
| 203 | -- | 219 | Jitendra Kanungo, Jitendra Raghuwanshi, Deepak Sharma, Sudeb Dasgupta. Energy Efficient Single Phase Adiabatic Logic and Its Application in Ripple Carry Adder Design |
| 220 | -- | 253 | Vassilis Alimisis, Vasileios Moustakas, Konstantinos Cheliotis, Christos Dimas, Paul P. Sotiriadis. A Power and Area Efficient Analog Classifier for Electrical Impedance Tomography Applications |
| 254 | -- | 277 | Xiaokun Lin, Bin Wang, Lu Liu, Xingchen Zhou, Weitao Yang, Hong Wang. 2/Ch 40 nm-CMOS 32-Channel Analog Front-End Acquisition Circuit with Analog-Domain Real-Time Offset Reduction and SS-ADC for LFP Neural Signal Recording |
| 278 | -- | 298 | Amit Gupta, Ashish Raman. Design and Large Signal Analysis of a 90 nm Novel CMOS Operational Trans-Resistance Amplifier |
| 299 | -- | 321 | Chandan Kumar Choubey, Manoj Kumar Tiwari, Aruna Pathak, Durgesh Nandan. Voltage Conveyor Transconductance Amplifier (VCTA): A Novel Analog Building Block for Advanced Analog Signal Processing Applications |
| 322 | -- | 342 | Tika Ram Pokhrel, Alaaddin Al-Shidaifat, Hanjung Song, Alak Majumder. Work Function Tuning in Strain Induced Double Gated Junctionless Transistor: A Device to Circuit Performance Study for Sub-20nm Nodes |
| 343 | -- | 363 | Abhishek Chauhan, Ashish Raman. Novel Charge Plasma Vertically Stacked Dopingless Nanosheet Field-Effect Transistor (DL-NSFET): Proposal and Extensive Analysis |
| 364 | -- | 392 | Barnali Chowdhury, Shashank Awasthi, Sanjeev Kumar Metya. i * j) Reversible RAM |
| 393 | -- | 417 | Vijay Pratap Yadav, Vipin Kumar Singh 0002, Ashish Ranjan Kumar, Tika Ram Pokhrel, Sanjeev Kumar Metya, Alak Majumder. Dynamic Header Switch to Influence Switching Current Profile of an IC Chip |
| 418 | -- | 439 | Lianyou Lai, Yazhe Zhang, Ling Qin, Weijian Xu. FiSA: Efficient Fixed-Point Stream Architecture for FastICA Implementing on FPGA |
| 440 | -- | 463 | Rongkun Wang, Dong Wang 0013, Wenjie Huang, Liming Song. Available Residual Capacity Prediction Model for the Life Cycle of Storage Battery Considering Multiple Disturbances |
| 464 | -- | 495 | Zhihao Chen, Tian Ban. Miniaturization of Insertable Cardiac Monitor: ECG Signal Processing Based on Stochastic Computing |
| 496 | -- | 511 | Keshan Deng, Jianqiong Zhang, Jiefeng Zang. Single-Channel Communication Signal Source Estimation Algorithm Based on Diagonal Loading |
| 512 | -- | 534 | Surbhi Bhatia Khan, A. Balajee, S. Sheik Mohideen Shah, T. R. Mahesh 0001, Mohammed Alojail, Indrajeet Gupta. A Novel Ensemble Empirical Decomposition and Time-Frequency Analysis Approach for Vibroarthrographic Signal Processing |
| 535 | -- | 556 | Anirban Tarafdar, Alak Majumder, Biman Debbarma, Bidyut K. Bhattacharyya. An Approach of ISI Elimination and High-Speed Data Reconstruction in Lossy On-Chip Serial Link |
| 557 | -- | 573 | Wilfred Kisku, Amandeep Kaur 0005, Deepak Mishra 0003. Efficient Edge-AI with Binarized Neural Networks and CMOS Image Sensors: A Sparsity-Driven Approach |
| 574 | -- | 595 | Munshi Mostafijur Rahaman, Prasun Ghosal, Chandan Giri. A Performance-Centric Topology for Hybrid Wireless-Network-on-Chip |
| 596 | -- | 620 | P. Gowtham, A. Anita Angeline, P. Sasipriya. Design and Analysis of a High-Speed Approximate Restoring Array Based Log Divider (ARLD) |
| 621 | -- | 646 | S. Harichandra Prasad, K. Kumar. Performance Analysis of Low Power Inexact Recursive Multipliers for Image Processing Applications |
| 647 | -- | 663 | Kattekola Naresh, Y. Padma Sai, Ch. Ganesh, Shubhankar Majumdar. Design of Logic Level Pruning Approximate Arithmetic Circuits Using TIGFET |
| 664 | -- | 702 | Sudhanshu Janwadkar, Rasika Dhavse. Approximate Vedic Multiplier Based Digital Filter Architecture for Portable Biomedical Signal Acquisition |