External Links

    Journal: Formal Methods in System Design

    Volume 9, Issue 3

    139 -- 188Alexandre Yakovlev, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis
    189 -- 233Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Marta Pietkiewicz-Koutny. On the Models for Asynchronous Circuit Behaviour with OR Causality
    235 -- 261Leo Marcus. The Incorporation of Testing into Formal Verification: Direct, Modular, and Hierarchical Correctness Degrees
    263 -- 302Tommaso Bolognesi. Regrouping Parallel Processes
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