Journal: Formal Methods in System Design

Volume 9, Issue 3

139 -- 188Alexandre Yakovlev, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis
189 -- 233Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Marta Pietkiewicz-Koutny. On the Models for Asynchronous Circuit Behaviour with OR Causality
235 -- 261Leo Marcus. The Incorporation of Testing into Formal Verification: Direct, Modular, and Hierarchical Correctness Degrees
263 -- 302Tommaso Bolognesi. Regrouping Parallel Processes

Volume 9, Issue 1/2

7 -- 40Kurt Jensen. Condensed State Spaces for Symmetrical Coloured Petri Nets
41 -- 75C. Norris Ip, David L. Dill. Better Verification Through Symmetry
77 -- 104Edmund M. Clarke, Somesh Jha, Reinhard Enders, Thomas Filkorn. Exploiting Symmetry in Temporal Logic Model Checking
105 -- 131E. Allen Emerson, A. Prasad Sistla. Symmetry and Model Checking