| 1141 | -- | 0 | Tetsuya Iida. Special Section on Analog Circuits and Related SoC Integration Technologies |
| 1142 | -- | 1148 | Masoud Zargari, David Su. Challenges in Designing CMOS Wireless Systems-on-a-Chip |
| 1149 | -- | 1155 | Atsushi Iwata, Takeshi Yoshida, Mamoru Sasaki. Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices |
| 1156 | -- | 1164 | Young-Chan Jang, Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong June Park. An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator |
| 1165 | -- | 1171 | Masaya Miyahara, Akira Matsuzawa. The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time |
| 1172 | -- | 1180 | Yusuke Ikeda, Akira Matsuzawa. Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC |
| 1181 | -- | 1188 | Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada. A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm |
| 1189 | -- | 1196 | Koichiro Noguchi, Takushi Hashida, Makoto Nagata. On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration |
| 1197 | -- | 1202 | Shiro Dosho, Naoshi Yanagisawa, Kazuaki Sogawa, Yuji Yamada, Takashi Morie. An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter |
| 1203 | -- | 1208 | Hitoshi Hayashi, Munenari Kawashima, Tadao Nakagawa, Kazuhiro Uehara, Yoshihiro Takigawa. An Active Terminal Circuit and Its Application to a Distributed Amplifier |
| 1209 | -- | 1221 | Toshifumi Nakatani, Koichi Ogawa. IM3 Cancellation Method Using Current Feedback Suitable for a Multi-Stage RFIC Amplifier |
| 1222 | -- | 1227 | Hitoshi Hayashi, Tadao Nakagawa, Kazuhiro Uehara, Yoshihiro Takigawa. Miniaturized Broadband Lumped-Element In-Phase Power Dividers |
| 1228 | -- | 1233 | Satoshi Kurachi, Toshihiko Yoshimasu, Haiwen Liu, Nobuyuki Itoh, Koji Yonemura. A SiGe BiCMOS VCO IC with Highly Linear Kvco for 5-GHz-Band Wireless LANs |
| 1234 | -- | 1240 | Mohammad B. Vahidfar, Omid Shoaei. A New Inductor-Less IP2 Enhancement Technique for CMOS Multi-Standard Mixer |
| 1241 | -- | 1246 | Toshiya Mitomo, Osamu Watanabe, Ryuichi Fujimoto, Shunji Kawaguchi. A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage |
| 1247 | -- | 1252 | Osamu Watanabe, Rui Ito, Shigehito Saigusa, Tadashi Arai, Tetsuro Itakura. A Fast ::::f::c:::::: Automatic Tuning Circuit with Wide Tuning Range for WCDMA Direct Conversion Receiver Systems |
| 1253 | -- | 1257 | Mohsen Asloni, Khayrollah Hadidi, Abdollah Khoei. Design of a New Folded Cascode Op-Amp Using Positive Feedback and Bulk Amplification |
| 1258 | -- | 1266 | Mahdi Mottaghi-Kashtiban, Abdollah Khoei, Khayrollah Hadidi. A Current-Mode, First-Order Takagi-Sugeno-Kang Fuzzy Logic Controller, Supporting Rational-Powered Membership Functions |
| 1267 | -- | 1273 | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera. Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling |
| 1274 | -- | 1281 | Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera. Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver |
| 1282 | -- | 1290 | Kouji Ichikawa, Yuki Takahashi, Makoto Nagata. Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements |
| 1291 | -- | 1298 | Naoyuki Unno, Nobuo Fujii. Automated Design of Analog Circuits Accelerated by Use of Simplified MOS Model and Reuse of Genetic Operations |
| 1299 | -- | 1303 | Yohei Fukumizu, Naoki Gochi, Makoto Nagata, Kazuo Taki. A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System |
| 1304 | -- | 1306 | Toru Choi, Tatsuya Sakamoto, Yasuhiro Sugimoto. A Study to Realize a 1-V Operational Passive Sigma-Delta Modulator by Using a 90 nm CMOS Process |
| 1307 | -- | 1310 | Yukinobu Makihara, Masayuki Ikebe, Eiichi Sano. Evaluation of Digitally Controlled PLL by Clock-Period Comparison |
| 1311 | -- | 1314 | Philipus Chandra Oh, Akira Matsuzawa, Win Chaivipas. A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter |
| 1315 | -- | 1317 | Takeshi Koike, Hiroki Sato, Akira Hyogo, Keitaro Sekine. A High Impedance Current Source Using Active Resistor |
| 1318 | -- | 1323 | Katsumi Morishita, Akihiro Kaino. Influence of Residual Stress on Post-Fabrication Resonance Wavelength Trimming of Long-Period Fiber Gratings by Heating |
| 1324 | -- | 1328 | Hiroyuki Okamoto, Masanobu Haraguchi, Toshihiro Okamoto, Masuo Fukui. Characteristics of an Optical Filter Composed of Two Vertically Coupled Microring Resonators |
| 1329 | -- | 1335 | Tomohiko Kanie, Hiroaki Kato, Yuichi Noro, Takashi Takeo, Kiwamu Oda, Haruhiko Ito. Study on Transmission Characteristics of Transformers of a RF Splitter |
| 1336 | -- | 1343 | Toshitaka Yamakawa, Takahiro Inoue, Masayuki Harada, Akio Tsuneda. Design of a CMOS Heartbeat Spike-Pulse Detection Circuit Integrable in an RFID Tag for Heart Rate Signal Sensing |