468 | -- | 0 | Akira Hyogo. Foreword |
469 | -- | 475 | Hirofumi Shinohara. Extremely Low Power Digital and Analog Circuits |
476 | -- | 485 | Kosuke Katayama, Mizuki Motoyoshi, Kyoya Takano, Chen Yang Li, Shuhei Amakawa, Minoru Fujishima. E-Band 65nm CMOS Low-Noise Amplifier Design Using Gain-Boost Technique |
486 | -- | 494 | Takeshi Mitsunaka, Masafumi Yamanoue, Kunihiko Iizuka, Minoru Fujishima. 8-GHz Locking Range and 0.4-pJ Low-Energy Differential Dual-Modulus 10/11 Prescaler |
495 | -- | 504 | Sho Ikeda, Sang-yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu. A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS |
505 | -- | 511 | Lechang Liu, Keisuke Ishikawa, Tadahiro Kuroda. Parametric Resonance Based Frequency Multiplier for Sub-Gigahertz Radio Receiver with 0.3V Supply Voltage |
512 | -- | 518 | Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa. A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit |
519 | -- | 525 | Mungyu Kim, Hoon-Ju Chung, Young-Chan Jang. A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications |
526 | -- | 537 | I-Jen Chao, Ching-Wen Hou, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang. A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder |
538 | -- | 545 | An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, Soon-Jyh Chang. A Low-Cost Stimulus Design for Linearity Test in SAR ADCs |
546 | -- | 556 | Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi. Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator |
557 | -- | 565 | Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata. Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking |
566 | -- | 574 | Shun-Ping Xiao, Si-Wei Chen, Yu-Liang Chang, Yong-Zhen Li, Motoyuki Sato. Polarimetric Coherence Optimization and Its Application for Manmade Target Extraction in PolSAR Data |
575 | -- | 582 | Yuto Kato, Masahiro Horibe. Comparison of Calculation Techniques for Q-Factor Determination of Resonant Structures Based on Influence of VNA Measurement Uncertainty |
583 | -- | 591 | Hiroyuki Takahashi, Toshihiko Kosugi, Akihiko Hirata, Jun Takeuchi, Koichi Murata, Naoya Kukutsu. 120-GHz-Band Amplifier Module with Hermetic Sealing Structure for 10-Gbit/s Wireless System |
592 | -- | 598 | Masato Nakamura, Junya Sekikawa. Real Time Spectroscopic Observation of Contact Surfaces Being Eroded by Break Arcs |
599 | -- | 608 | Junichi Hirase. Verification of Moore's Law Using Actual Semiconductor Production Data |
609 | -- | 618 | Junichi Hirase. Introduction of Yield Quadrant and Yield Capability Index for VLSI Manufacturing |
619 | -- | 623 | Ming-Hsien Shih, Chia-Ling Wei. Design of a Boost DC-DC Converter for RGB LED Driver |