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    Journal: it - Information Technology

    Volume 56, Issue 4

    147 -- 0Paul Molitor. Preface
    148 -- 149Rolf Drechsler. Testing integrated circuits
    150 -- 156Sudhakar M. Reddy, Zhuo Zhang. On achieving minimal size test sets for scan designs
    157 -- 164Stephan Eggersglüß, Rolf Drechsler. An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
    165 -- 172Sybille Hellebrand, Hans-Joachim Wunderlich. SAT-based ATPG beyond stuck-at fault testing
    173 -- 181Jean Marc Gallière, Florence Azaïs, Mariane Comte, Michel Renovell. Testing for gate oxide short defects using the detectability interval paradigm
    182 -- 191Te-Hsuan Chen, Armin Alaghi, John P. Hayes. Behavior of stochastic circuits under severe error conditions
    192 -- 202Ilia Polian. Hardware security and test: Friends or enemies?
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