Journal: JETC

Volume 13, Issue 2

0 -- 0Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié. Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices
0 -- 0Hang Zhang, Xuhao Chen, Nong Xiao, Lei Wang, Fang Liu, Wei Chen 0009, Zhiguang Chen. Shielding STT-RAM Based Register Files on GPUs against Read Disturbance
0 -- 0Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel. A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits
0 -- 0Yao Wang, Liang Rong, Haibo Wang, Guangjun Wen. One-Step Sneak-Path Free Read Scheme for Resistive Crossbar Memory
0 -- 0Wei Jiang, Liang Wen, Ke Jiang, Xia Zhang, Xiong Pan, Keran Zhou. System-Level Design to Detect Fault Injection Attacks on Embedded Real-Time Applications
0 -- 0José L. Abellán, Chao Chen, Ajay Joshi. Electro-Photonic NoC Designs for Kilocore Systems
0 -- 0Yan Fang, Victor V. Yashin, Brandon B. Jennings, Donald M. Chiarulli, Steven P. Levitan. A Simplified Phase Model for Simulation of Oscillator-Based Computing Systems
0 -- 0Arnab Kumar Biswas. Source Authentication Techniques for Network-on-Chip Router Configuration Packets
0 -- 0Abdullah Guler, Niraj K. Jha. Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs
0 -- 0A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy 0001. Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes
0 -- 0Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda. A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors
0 -- 0Joydeep Rakshit, Kartik Mohanram, Runlai Wan, Kai-Tak Lam, Jing Guo. Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems
0 -- 0Xuan Wang 0001, Jiang Xu 0001, Zhe Wang 0003, Haoran Li, Peng Yang 0003, Luan H. K. Duong, Rafael K. V. Maeda, Zhifei Wang. Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign
0 -- 0Anderson L. Sartor, Arthur Francisco Lorenzon, Luigi Carro, Fernanda Lima Kastensmidt, Stephan Wong, Antonio C. S. Beck. Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors
0 -- 0Sparsh Mittal. A Survey of Techniques for Architecting Processor Components Using Domain-Wall Memory
0 -- 0Aida Todri-Sanial, Saraju P. Mohanty, Mariane Comte, Marc Belleville. Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era
0 -- 0Meghna G. Mankalale, Sachin S. Sapatnekar. Optimized Standard Cells for All-Spin Logic
0 -- 0Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy 0001. Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC