Journal: Journal of Systems Architecture

Volume 39, Issue 2-5

0 -- 0Benny Graft Mortensen, Ferenc Vajda. Preface
59 -- 63Miroslaw Thor, Tomasz Kalinowski. HP-MODTRANS: A High performance modular transputer architecture
65 -- 68J. Hernandez, Pedro de Miguel, Manuel Barrena García, Juan Miguel Martínez, Antonio Polo Márquez, Manuel M. Nieto Rodríguez. Implementation details of ALBA in a transputer machine
69 -- 74András Pataricza, István Majzik, Wolfgang Hohl, Joachim Hönig. Watchdog processors in parallel systems
75 -- 78Fleur L. Steven, R. G. Adams, Gordon B. Steven, L. Wang, D. J. Whale. Addressing mechanisms for VLIW and superscalar processors
79 -- 82Péter Kacsuk. Memory management in LOGFLOW
83 -- 86Jordi Tubella, Antonio González. MEM: A new execution model for Prolog
89 -- 92Anna Antola, Fausto Distante, Andrea Marchese. High level synthesis through folding of data flow graphs: Optimal intra-node scheduling
93 -- 96Mary Buchanan, Bob Dickerson, Carol Britton, Martin Loomes. Using CCS for the specification of inheritance
97 -- 100Maximilian Frey, Andreas Weininger. Using temporal logic specifications to debug parallel programs
101 -- 104Won-Yong Kim, Yoon-Joon Lee, Joon Ho Lee, Young Hwa Cho. The fuzzy set model based on N-ary positively compensatory operators
105 -- 108Joon Ho Lee, Myoung-Ho Kim, Young Hwa Cho. Using term dependencies of a thesaurus in the fuzzy set model
111 -- 114Francisco Guerra Santana, Sergio Arévalo, Angel Alvarez, Javier Miranda. A quick distributed consensus protocol
115 -- 118Janusz Sosnowski, Anna Derezinska, Ilona Bluemke. Autodiagnostics for transputer systems
119 -- 124Stergios Papadimitriou, Achilles Kameas, Georgios Pavlides. Determining effective multiprocessor scheduling policies for repetitive real-time tasks
125 -- 128Josep-Lluis Larriba-Pey, Angel Jorba, Juan J. Navarro. Spike Algorithm with savings for strictly diagonal dominant tridiagonal systems
129 -- 132Peter Milligan, T. J. G. Benson, R. K. McConnell, A. Rea. Process to processor mapping within the mathematician s Devil
139 -- 142A. del Río, P. Mariño. A rule based programming language for real-time applications
143 -- 146Tatjana Kapus, Bogomir Horvat, Marjeta Pucko. A true concurrency semantics for parallel programs
147 -- 150Tamás Gaál. Parallel compiler generation
151 -- 154Miroslav Svéda. Language prototyping with attribute grammars and macros
155 -- 158Hongwoo Nam, Songchun Moon. Global deadlock detection for concurrency control in multidatabase systems
161 -- 164Wojciech Cellary, Waldemar Wieczerzycki. Locking in DAG-structured databases
165 -- 168Doheon Lee, Myoung-Ho Kim. Extending semantics of relational operators for vague queries
169 -- 172G. Moreno, P. González, J. A. Gámez. Parallel algorithm for table division in relational databases
173 -- 176Dongwook Shin, Yongun Yoon, Key-Sun Choi. The performance evaluation of a knowledge-based information retrieval system
177 -- 180Byungwook Kim, Songchun Moon. A flexible indexing structure supporting multi-attribute database applications: MAIN
183 -- 186Denis Trcek, Borka Jerman-Blazic. Certificates handling and their support within X.500 system
187 -- 190P. Mariño, A. del Río. An accurate and fast CSMA/CD simulator
191 -- 194Sarolta Dibuz. A frame-based approach to conformance testing
195 -- 198Marjeta Pucko, Gorazd Kandus. Service-driven protocol synthesis for specific users
201 -- 204Carlos F. Alastruey, José Ramón González de Mendívil. Advances in adaptive simulation of interconnected systems with delays
205 -- 208Leszek Borzemski, D. Gajewski, S. Glowacz, M. Szczypinski, K. Wojtczak. A load balancing system for unix-based local area networks
209 -- 212Juan Carlos Calderón, JoséRamón Salvador, Rafael Valle, Luis París, Carles Ferrer. Multi-protocol communications controller
213 -- 216Monika Kapus-Kolar. Derivation of protocols implementing services with event priorities
217 -- 220Jonghyun Lee, Songchun Moon. Architecture for interoperability of network management systems in multi-domain network
223 -- 227Heping He, Hussein Zedan. Cycle calculus for hybrid systems
229 -- 232Willem Jan Withagen, Rob Takken. Hierachical modeling and simulation of processor architectures
233 -- 236R. Moreno, Román Hermida, Daniel Mozos, Katzalin Olcoz. Global hardware synthesis guided by realistic probability computation
237 -- 240M. G. Sami, Donatella Sciuto, Renato Stefanelli. Concurrently self-checking structures for Fsms
241 -- 244George-Peter K. Economou, Spiridon Nikolaidis, D. E. Metafas, Constantinos E. Goutis. Development of a technology independent library
245 -- 248F. C. Blom, J. Oliver, M. Rullán, C. Ferrer. Testability enhancement using physical design rules in a CMOS cell library
251 -- 254Labros Bisdounis, Dimitris Metafas, A. M. Maras, C. Mavridis. VLSI implementation of digit-serial arithmetic modules
255 -- 258Lluis Ribas, Jordi Riera, J. M. Pérez, Joaquín Saiz, Jordi Carrabina, Lluís Terés. Automatic pattern generation for the electrical characterization of digital modules
259 -- 262A. K. Betts, Ivo Bolsens, E. Sicard, Marc Renaudin, Adrian Johnstone. SMILE: A scalable microcontroller library element
263 -- 266Katzalin Olcoz, Francisco Tirado, Daniel Mozos, Julio Septién, R. Moreno. Data path structures and heuristics for testable allocation in high level synthesis
267 -- 270L. Gómez, A. Hernández, A. Nunez. Multiobjective optimization using analytical models of GaAs high-speed digital circuits
273 -- 276Dieter Welzel, Hans-Ludwig Hausen. A five step method for metric-based software evaluation - effective software metrication with respect to quality standards
277 -- 280I. del Campo, José Ramón González de Mendívil, José Manuel Tarela. Development of a fuzzy logic controller on a digital signal processor
281 -- 284Zdenek Blazek. Monitoring and data recording system for the underground
285 -- 288A. Dékány, I. Erényi, Sándor Fejes. High-speed parallel implementation of the statistical feature matrix method

Volume 39, Issue 1

1 -- 15Seong Baeg Kim, Myung Soon Park, Sun-Ho Park, Sang Lyul Min, Heonshik Shin, Chong-Sang Kim, Deog Kyoon Jeong. Threaded prefetching: An adaptive instruction prefetch mechanism
17 -- 23V. A. Spais, L. P. Petrou. Implementation of the robot inverse dynamics computation algorithm on a transputer network
25 -- 41Bogong Su, Jian Wang, Zhizhong Tang, Chihong Zhang, Wei Zhao. URPR-1: A single-chip VLIW architecture
43 -- 53Jie Wu, Eduardo B. Fernández. Broadcasting in faulty hypercubes