657 | -- | 674 | Krishna M. Kavi, Ali R. Hurson. Design of cache memories for dataflow architecture |
675 | -- | 690 | C. E. Prakash, Swami Manohar. Hardware architecture for voxelization-based volume rendering of unstructured grids |
691 | -- | 702 | M. J. Kumar, Lalit M. Patnaik, B. Nag. Fault-tolerant message routing in the extended hypercube |
703 | -- | 721 | Evgenia Smirni, Emilia Rosti, Lawrence W. Dowdy, Giuseppe Serazzi. A methodology for the evaluation of multiprocessor non-preemptive allocation policies |
723 | -- | 735 | Jeong-Ki Kim, Jae-Woo Chang. Horizontally divided signature files on a parallel machine architecture |
737 | -- | 754 | Jovan Djordjevic, Milo Tomasevic, Miroslav Bojovic, Veselin Potic, Sinisa Randjic. An operating system accelerator |
755 | -- | 772 | Gi-Ho Park, Oh-Young Kwon, Tack-Don Han, Shin-Dug Kim, Sung-Bong Yang. Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors |
773 | -- | 786 | Pedro Tabuenca, Pablo Sánchez, Eugenio Villar. An algorithm for clock cycle selection in behavioral synthesis |
787 | -- | 802 | Nam-Kyu Lee, Sung-Bong Yang, Tack-Don Han, ShinDug Kirn. Modeling and performance analysis of dual head disk structure |
803 | -- | 814 | Fabio Ancona, Rodolfo Zunino. Hypercube structures with high-connectivity supporting nodes |
815 | -- | 830 | P. L. López, Rosa Alcover, José Duato, Luisa Zúnica. A cost-effective methodology for the evaluation of interconnection networks |