| 423 | -- | 425 | José E. Schutt-Ainé, Sung-Mo Kang. Interconnections-addressing the next challenge of IC technology (part I: integration and packaging trends) |
| 426 | -- | 443 | Barry K. Gilbert, Michael J. Degerstrom, Patrick J. Zabinski, Thimothy M. Schafer, Gregg J. Fokken, Barbara A. Randall, Daniel J. Schwab, Erik S. Daniel, Scott C. Sommerfeldt. Emerging multigigahertz digital and mixed-signal integrated circuits targeted for military applications: dependence on advanced electronic packaging to achieve full performance |
| 444 | -- | 455 | Robert C. Frye. Integration and electrical isolation in CMOS mixed-signal wireless chips |
| 456 | -- | 466 | Mau-Chung Frank Chang, Vwani P. Roychowdhury, Liyang Zhang, Hyunchol Shin, Yongxi Qian. RF/wireless interconnect for inter- and intra-chip communications |
| 467 | -- | 489 | Dennis Sylvester, Kurt Keutzer. Impact of small process geometries on microarchitectures in systems on a chip |
| 490 | -- | 504 | Ron Ho, Kenneth Mai, Mark A. Horowitz. The future of wires |
| 505 | -- | 528 | Jason Cong. An interconnect-centric design flow for nanometer technologies |
| 529 | -- | 555 | Alina Deutsch, Paul W. Coteus, Gerard V. Kopcsay, Howard H. Smith, Christopher W. Surovic, Byron Krauter, Daniel C. Edelstein, Phillip L. Restle. On-chip wiring design challenges for gigahertz operation |
| 556 | -- | 573 | Fabrice Caignet, Sonia Delmas-Bendhia, Etienne Sicard. The challenge of signal integrity in deep-submicrometer CMOS technology |
| 574 | -- | 576 | Brian Bowers. Volta and the continuous electric current |