Journal: SIGARCH Computer Architecture News

Volume 19, Issue 6

4 -- 8Henry G. Baker. Precise instruction scheduling without a precise machine model
9 -- 11Robert McLaughlin. Look-ahead branching hardware
12 -- 16Thomas Beth, Volker Hatz. A restricted crossbar implementation and its applications
19 -- 23Mark Thorson. Usenet nuggets
24 -- 25Robert Bernecky. Book review: Past, Present, Parallel: A Survey of Available Parallel Computing Systems by Arthur Trew & Greg Wilson (Eds.), (Springer-Verlag 1991)

Volume 19, Issue 5

7 -- 0David A. Patterson. Towards guidelines for SIGARCH sponsored conferences
10 -- 0Yeong-Chang Maa, Dhiraj K. Pradhan, Dominique Thiébaut. Two economical directory schemes for large-scale cache coherent multiprocessors
21 -- 26Mark Thorson. Usenet Nuggets
27 -- 29Vladimir G. Ivanovíc. Book review: Computation Structures by Stephen A Ward and Robert H. Halstead, Jr. (MIT Press or McGraw-Hill, 1990)
27 -- 29Moshe Krieger. Book review: Multiprocessors by D. Tabak (Prentice-Hall, 1990)
29 -- 30John Fulcher. Book review: The 68000 and 68020 Microprocessors: Hardware, Software and Interfacing Techniques by W. Triebel and A. Singh (Prentice Hall, 1991)

Volume 19, Issue 4

6 -- 13Paul R. Wilson. Pointer swizzling at page fault time: efficiently supporting huge address spaces on standard hardware
14 -- 29Morihiro Kuga, Kazuaki Murakami, Shinji Tomita. DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture
30 -- 36Carl Ponder. Performance variation across benchmark suites
37 -- 44Thomas M. Conte, Wen-mei W. Hwu. A brief survey of benchmark usage in the architecture community
45 -- 65Todd D. Morris, Edward F. Gehringer. A cost-effective reliable multipath interconnection network
66 -- 68Phillip A. Laplante. An improved conditional branching scheme for a single instruction computer architecture
69 -- 79Andrew J. DuBois, John Rasure. Design and evaluation of a distributed asynchronous VLSI crossbar switch controller for a packet switched supercomputer network
80 -- 85Stanley E. Lass. The compiler controlled pack cache and messaging
86 -- 93Theo Ungerer, Eberhard Zehendner. A multi-level parallelism architecture
94 -- 108Wolfgang Matthes. How many operation units are adequate?
109 -- 116Alberto R. Cunha, Carlos N. Ribeiro, José A. Marques. The architecture of a memory management unit for object-oriented systems
117 -- 123Norman Matloff. An argument against scalable cache coherency
124 -- 131D. P. Rodohan, Ray J. Glover. An overview of the A architecture for optimisation problems in a logic programming environment
132 -- 137Stuart C. Wray. Time-sequenced DMA for multimedia computers
138 -- 153Ganesh Ramamoorthy, Alok N. Choudhary. A bibliography for multiprocessor cache memories
154 -- 182Alan Jay Smith. Second bibliography on Cache memories
185 -- 191Mark Thorson. Usenet Nuggets

Volume 19, Issue 1

5 -- 0Frank Thomson Leighton. Selected Papers from the Symposium on Parallel Algorithms and Architectures
6 -- 14John Y. Ngai, Charles L. Seitz. A framework for adaptive routing in multicomputer networks
15 -- 24Richard Beigel, Clyde P. Kruskal. Processor networks and interconnection networks without long wires (extended abstract)
25 -- 34Fred S. Annexstein. Fault tolerance in hypercube-derivative networks (preliminary version)
35 -- 44Richard M. Fujimoto. The virtual machine
45 -- 52Gianfranco Bilardi, Scot W. Hornick, Majid Sarrafzadeh. Optimal VLSI architectures for multidimensional DFT (preliminary version)
53 -- 60Clark D. Thomborson, Belle W. Y. Wei. Systolic implementations of a move-to-front text compressor
61 -- 68Thomas F. Knight Jr.. Technologies for low latency interconnection switches
69 -- 78Martin C. Herbordt, Charles C. Weems, James C. Corbett. Message-passing algorithms for a SIMD torus with coteries
79 -- 88Smaragda Konstantinidou, Lawrence Snyder. The chaos router: a practical application of randomization in network routing
89 -- 96Jehoshua Bruck, Robert Cypher, Danny Soroker. Running algorithms efficiently on faulty hypercubes (extended abstract)
97 -- 105Naomi Nishimura. Asynchronous shared memory parallel computation (preliminary version)
106 -- 113Mark Shand, Patrice Bertin, Jean Vuillemin. Hardware speedups in long integer multiplication
114 -- 119Manu Thapar, Bruce Delagi. Cache coherence for large scale shared memory multiprocessors
120 -- 127Peter Grabienski. FLIP-FLOP: a stack-oriented multiprocessing system
128 -- 134Camille C. Price. Task allocation in data flow multiprocessors: an annotated bibliography
135 -- 142Rod Adams, Gordon B. Steven. A parallel pipelined processor with conditional instruction execution
146 -- 150Mark Thorson. Usenet Nuggets
151 -- 0Michael L. Hilton. Book review: Systems Programming in Parallel Logic Languages by lan Foster (Prentice Hall, 1990)
152 -- 153Keith Anthony. Book review: Technology Projection Modeling of Future Computer Systems by Al Cutaia (Prentice-Hall, 1990)
153 -- 154Paul B. Schneck. Book review: Optimizing FORTRAN Programs by C. F. Schofield (Halstead Press, 1989)
154 -- 156Robert Bernecky. Book review: Multiprocessors by Daniel Tabak (Prentice Hall, Englewood Cliffs, NJ)
156 -- 157Robert Bernecky. Book review: Multiprocessor Performance by Erol Gelenbe (J. Wiley & Sons, Chichester, England)
157 -- 158John Fulcher. Book review: Neural Net Applications and Products by Richard K. Miller, Terri C. Walker, and Anne M. Ryan (SEAl Technical Publications, 1990)