Journal: SIGARCH Computer Architecture News

Volume 27, Issue 5

1 -- 5Marc Torrant, Muhammad Shaaban, Roy Czernikowski, Kenneth W. Hsu. A simultaneous multithreading simulator
6 -- 10Mark Thorson. Internet Nuggets

Volume 27, Issue 4

2 -- 5Philip Machanick. Correction to RAMpage ASPOLOS paper
6 -- 11Hadi Shahriar Shahhoseini, M. Naderi, S. Nemati. Achieving the best performance on superscalar processors
12 -- 14Mark Thorson. Internet Nuggets

Volume 27, Issue 3

1 -- 3. In memoriam - SIGARCH founder: Caxton C. Foster
4 -- 9Seung H. Hwang, Gwan S. Choi. Selective-set-invalidation (SSI) for soft-error-resilient cache architecture
10 -- 17Peng Cheng, Hai Jin, Jiangling Zhang. Design of high performance RAID in real-time system
18 -- 23C. K. Yuen. Architectural support for the cache based vector computation
24 -- 31Benjamin Driker. Disbursed control computer architecture
32 -- 37Humayun Khalid. Performance evaluation of multimedia systems with MPEG-2 bitstreams
38 -- 42Humayun Khalid. A methodology for performance evaluation of systems with large emulation code
43 -- 48Humayun Khalid. Tracing multimedia benchmarks with five degrees of validation
49 -- 52Humayun Khalid. Performance evaluation of two operating systems
53 -- 60Mark Thorson. Internet Nuggets

Volume 27, Issue 1

3 -- 9C. K. Yuen. Stack and RISC
10 -- 21Sandra Johnson Baylor. Unified scalable shared memory architectures
22 -- 0Anthony DeWitt, Thomas Gross. The potential of thread-level speculation based on value profiling
23 -- 26John Kalamatianos, David R. Kaeli. Improving the accuracy of indirect branch prediction via branch classification
27 -- 30Roy Dz-Ching Ju, Jean-Francois Collard, Karim Oukbir. Probabilistic memory disambiguation and its application to data speculation
31 -- 34Matthew A. Postiff, David A. Greene, Gary S. Tyson, Trevor N. Mudge. The limits of instruction level parallelism in SPEC95 applications
35 -- 38Byung-Sun Yang, Junpyo Lee, Jinpyo Park, Soo-Mook Moon, Kemal Ebcioglu, Erik R. Altman. Lightweight monitor for Java VM
39 -- 42Amit Rao, Santosh Pande. Storage assignment using expression tree transformations to generate compact and efficient DSP code
43 -- 46Krisztián Flautner, Gary S. Tyson, Trevor N. Mudge. A high level simulator integrated with the Mirv compiler
47 -- 50Hugues Cassé, L. Féraud, Christine Rochange, Pascal Sainrat. Using the abstract interpretation technique for static pointer analysis
51 -- 54R. Iris Bahar, Brad Calder, Dirk Grunwald. A comparison of software code reordering and victim buffers
55 -- 58Steve Carr, Philip H. Sweany. Improving software pipelining with hardware support for self-spatial loads