2 | -- | 7 | Marco Aurelio Nuño-Maganda, Cesar Torres-Huitzil. A temporal coding hardware implementation for spiking neural networks |
8 | -- | 13 | Hirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system |
14 | -- | 20 | Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk. Efficient reconfigurable design for pricing asian options |
21 | -- | 26 | Tadayoshi Horita, Itsuo Takanami. An FPGA-based fast classifier with high generalization property |
27 | -- | 32 | Andrew Putnam, Aaron Smith, Doug Burger. Dynamic vectorization in the E2 dynamic multicore architecture |
33 | -- | 39 | Jong Kyung Paek, Kiyoung Choi, Jong-eun Lee. Binary acceleration using coarse-grained reconfigurable architecture |
40 | -- | 45 | Keisuke Dohi, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri, Duncan A. Buell. Implementation of a programming environment with a multithread model for reconfigurable systems |
46 | -- | 52 | Mojtaba Sabeghi, Hamid Mushtaq, Koen Bertels. Runtime multitasking support on polymorphic platforms |
53 | -- | 59 | Kuen Hung Tsoi, Anson H. T. Tse, Peter Pietzuch, Wayne Luk. Programming framework for clusters with heterogeneous accelerators |
60 | -- | 65 | Claude Tadonki, Gilbert Grodidier, Olivier Pène. An efficient CELL library for lattice quantum chromodynamics |
66 | -- | 72 | Ryan Taylor, Xiaoming Li. Software-based branch predication for AMD GPUs |
73 | -- | 79 | Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, Radu Tudoran. Multipliers for floating-point double precision and beyond on FPGAs |
80 | -- | 86 | Kentaro Sano, Luzhou Wang, Satoru Yamamoto. Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation |
87 | -- | 92 | Chi Chiu Tsang, Hayden Kwok-Hay So. Dynamic power reduction of FPGA-based reconfigurable computers using precomputation |
93 | -- | 96 | Mark Thorson. Internet nuggets |