| 18 | -- | 0 | Per Stenström, Koen De Bosschere. Introduction to the special issue on high-performance and embedded architectures and compilers |
| 19 | -- | 0 | Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería. ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache |
| 20 | -- | 0 | Ali Galip Bayrak, Nikola Velickovic, Paolo Ienne, Wayne Burleson. An architecture-independent instruction shuffler to protect against side-channel attacks |
| 21 | -- | 0 | John Demme, Simha Sethumadhavan. Approximate graph clustering for program characterization |
| 22 | -- | 0 | Mihai Pricopi, Tulika Mitra. Bahurupi: A polymorphic heterogeneous multi-core architecture |
| 23 | -- | 0 | Jeroen V. Cleemput, Bart Coppens, Bjorn De Sutter. Compiler mitigations for time attacks on modern x86 processors |
| 24 | -- | 0 | Jason McCandless, David Gregg. Compiler techniques to improve dynamic branch prediction for indirect jump and call instructions |
| 25 | -- | 0 | Antonio García-Guirado, Ricardo Fernández Pascual, Alberto Ros, José M. García. DAPSCO: Distance-aware partially shared cache organization |
| 26 | -- | 0 | Zhenjiang Wang, Chenggang Wu, Pen-Chung Yew, Jianjun Li, Di Xu. On-the-fly structure splitting for heap objects |
| 27 | -- | 0 | Dibyendu Das, Benoît Dupont de Dinechin, Ramakrishna Upadrasta. Efficient liveness computation using merge sets and DJ-graphs |
| 28 | -- | 0 | George Patsilaras, Niket K. Choudhary, James Tuck. Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era |
| 29 | -- | 0 | Roman Malits, Evgeny Bolotin, Avinoam Kolodny, Avi Mendelson. Exploring the limits of GPGPU scheduling in control flow bound applications |
| 30 | -- | 0 | Lois Orosa, Elisardo Antelo, Javier D. Bruguera. FlexSig: Implementing flexible hardware signatures |
| 31 | -- | 0 | J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero. Hardware transactional memory with software-defined conflicts |
| 32 | -- | 0 | Yongjoo Kim, Jongeun Lee, Toan X. Mai, Yunheung Paek. Improving performance of nested loops on reconfigurable array processors |
| 33 | -- | 0 | Madhura Purnaprajna, Paolo Ienne. Making wide-issue VLIW processors viable on FPGAs |
| 34 | -- | 0 | Petar Radojkovic, Sylvain Girbal, Arnaud Grasset, Eduardo Quiñones, Sami Yehia, Francisco J. Cazorla. On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments |
| 35 | -- | 0 | Leonid Domnitser, Aamer Jaleel, Jason Loew, Nael B. Abu-Ghazaleh, Dmitry Ponomarev. Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks |
| 36 | -- | 0 | Alejandro Rico, Felipe Cabarcas, Carlos Villavieja, Milan Pavlovic, Augusto Vega, Yoav Etsion, Alex Ramírez, Mateo Valero. On the simulation of large-scale architectures using multiple application abstraction levels |
| 37 | -- | 0 | Selma Saidi, Pranav Tendulkar, Thierry Lepley, Oded Maler. Optimizing explicit data transfers for data parallel applications on the cell architecture |
| 38 | -- | 0 | Min Feng, Changhui Lin, Rajiv Gupta. PLDS: Partitioning linked data structures for parallelism |
| 39 | -- | 0 | Benoît Pradelle, Alain Ketterlin, Philippe Clauss. Polyhedral parallelization of binary code |
| 40 | -- | 0 | Yaozu Dong, Yu Chen, Zhenhao Pan, Jinquan Dai, Yunhong Jiang. ReNIC: Architectural extension to SR-IOV I/O virtualization for efficient replication |
| 41 | -- | 0 | Tom M. Bruintjes, Karel H. G. Walters, Sabih H. Gerez, Bert Molenkamp, Gerard J. M. Smit. Sabrewing: A lightweight architecture for combined floating-point and integer arithmetic |
| 42 | -- | 0 | Mario Kicherer, Fabian Nowak, Rainer Buchty, Wolfgang Karl. Seamlessly portable applications: Managing the diversity of modern heterogeneous systems |
| 43 | -- | 0 | Nathanael Premillieu, André Seznec. SYRANT: SYmmetric resource allocation on not-taken and taken paths |
| 44 | -- | 0 | William Hasenplaugh, Pritpal S. Ahuja, Aamer Jaleel, Simon C. Steely Jr., Joel S. Emer. The gradient-based cache partitioning algorithm |
| 45 | -- | 0 | Javier Lira, Timothy M. Jones, Carlos Molina, Antonio González. The migration prefetcher: Anticipating data promotion in dynamic NUCA caches |
| 46 | -- | 0 | Kishore Kumar Pusukuri, Rajiv Gupta, Laxmi N. Bhuyan. Thread Tranquilizer: Dynamically reducing performance variation |
| 47 | -- | 0 | Dong-song Zhang, Deke Guo, Fang-Yuan Chen, Fei Wu, Tong Wu, Ting Cao, Shiyao Jin. TL-plane-based multi-core energy-efficient real-time scheduling algorithm for sporadic tasks |
| 48 | -- | 0 | Michael J. Lyons, Mark Hempstead, Gu-Yeon Wei, David Brooks. The accelerator store: A shared memory framework for accelerator-based systems |
| 49 | -- | 0 | Daniel A. Orozco, Elkin Garcia, Rishi Khan, Kelly Livingston, Guang R. Gao. Toward high-throughput algorithms on many-core architectures |
| 50 | -- | 0 | Kevin Stock, Louis-Noël Pouchet, P. Sadayappan. Using machine learning to improve automatic vectorization |
| 51 | -- | 0 | Kanit Therdsteerasukdi, Gyungsu Byun, Jason Cong, M. Frank Chang, Glenn Reinman. Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system |
| 52 | -- | 0 | Frederick Ryckbosch, Stijn Polfliet, Lieven Eeckhout. VSim: Simulating multi-server setups at near native hardware speed |
| 53 | -- | 0 | Miao Zhou, Yu Du, Bruce R. Childers, Rami G. Melhem, Daniel Mossé. Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems |
| 54 | -- | 0 | Qingping Wang, Sameer Kulkarni, John Cavazos, Michael F. Spear. A transactional memory with automatic performance tuning |
| 55 | -- | 0 | Bartosz Bogdanski, Sven-Arne Reinemo, Frank Olaf Sem-Jacobsen, Ernst Gunnar Gran. sFtree: A fully connected and deadlock-free switch-to-switch routing algorithm for fat-trees |