| 385 | -- | 399 | Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli. Innovative Structures for CMOS Combinational Gates Synthesis |
| 400 | -- | 412 | Jien-Chung Lo. Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands |
| 413 | -- | 430 | John C. Ramirez, Rami G. Melhem. Computational Arrays with Flexible Redundancy |
| 431 | -- | 442 | Pradeep K. Dubey, George B. Adams III, Michael J. Flynn. Instruction Window Size Trade-Offs and Characterization of Program Parallelism |
| 443 | -- | 459 | Michael J. Corinthios. Optimal Parallel and Pipelined Processing Through a New Class of Matrices with Application to Generalized Spectral Analysis |
| 460 | -- | 469 | Vitit Kantabutra, Andreas G. Andreou. A State Assignment Approach to Asynchronous CMOS Circuit Design |
| 470 | -- | 475 | Annette Lagman, Walid A. Najjar, Pradip K. Srimani. An Analysis of Edge Fault Tolerance in Recursively Decomposable Regular Networks |
| 475 | -- | 480 | Shambhu J. Upadhyaya, Bina Ramamurthy. Concurrent Process Monitoring with No Reference Signatures |
| 480 | -- | 484 | Imrich Chlamtac, András Faragó. An Optimal Channel Access Protocol with Multiple Reception Capacity |
| 484 | -- | 489 | Shlomo Kipnis. Analysis of Asynchronous Binary Arbitration on Digital Transmission-Line Busses |
| 490 | -- | 495 | Steven W. Burns, Niraj K. Jha. A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme |
| 495 | -- | 501 | Shih-Yuang Su, Cheng-Wen Wu. Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns |
| 501 | -- | 506 | Spencer W. Ng, Richard L. Mattson. Uniform Parity Group Distribution in Disk Arrays with Multiple Failures |
| 507 | -- | 512 | Chien-In Henry Chen, Anup Kumar. Comments on Area-Time Optimal Adder Design |