245 | -- | 249 | Socheat Heng, Cong-Kha Pham. A Low-Power High-PSRR Low-Dropout Regulator With Bulk-Gate Controlled Circuit |
250 | -- | 254 | Annajirao Garimella, M. Wasequr Rashid, Paul M. Furth. Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO |
255 | -- | 259 | Chi-En Liu, Yi-Jhan Hsieh, Jean-Fu Kiang. RFID Regulator Design Insensitive to Supply Voltage Ripple and Temperature Variation |
260 | -- | 264 | Mehdi Kiani, Maysam Ghovanloo. An RFID-Based Closed-Loop Wireless Power Transmission System for Biomedical Applications |
265 | -- | 269 | Chua-Chin Wang, Chih-Lin Chen, Ron-Chi Kuo, Doron Shmilovitz. Self-Sampled All-MOS ASK Demodulator for Lower ISM Band Applications |
270 | -- | 274 | Nitesh Singhal, Sudhakar Pamarti. A Digital Envelope Combiner for Switching Power Amplifier Linearization |
275 | -- | 279 | Gordana Jovanovic-Dolecek, Massimiliano Laddomada. An Economical Class of Droop-Compensated Generalized Comb Filters: Analysis and Design |
280 | -- | 284 | Gabriel Torrens, Bartomeu Alorda, Salvador Barcelo, José Luis Rosselló, Sebastiàn A. Bota, Jaume Segura. Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination |
285 | -- | 289 | Pramod Kumar Meher. LUT Optimization for Memory-Based Computation |
290 | -- | 294 | Stuart N. Wooters, Benton H. Calhoun, Travis N. Blalock. An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS |
295 | -- | 299 | Alexandru Amaricai, Mircea Vladutiu, Oana Boncalo. Design Issues and Implementations for Floating-Point Divide-Add Fused |
300 | -- | 304 | Xi Chen, Siu Chung Wong, Chi Kong Tse. Adding Randomness to Modeling Internet TCP-RED Systems With Interactive Gateways |
305 | -- | 309 | Alexander Jimenez Triana, Wallace Kit-Sang Tang, Guanrong Chen, Alain Gauthier. Chaos Control in Duffing System Using Impulsive Parametric Perturbations |
310 | -- | 314 | Rui Wang, Bo Wang, Guo-Ping Liu, Wei Wang 0036, David Rees. infty Controller Design for Networked Predictive Control Systems Based on the Average Dwell-Time Approach |