| 237 | -- | 241 | Marco Crepaldi, Danilo Demarchi. 2 Ring-Oscillator-Based Self-Calibrating IR-UWB Transmitter Using an Asynchronous Logic Duty-Cycled PLL |
| 242 | -- | 246 | Imad ud Din, Johan Wernehag, Stefan Andersson, Sven Mattisson, Henrik Sjöland. Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS |
| 247 | -- | 251 | Wonhoon Jang, Nelson Silva, Arnaldo Oliveira, Nuno Borges Carvalho. Designing Harmonic-Controlled Drivers for Switching Power Amplifiers |
| 252 | -- | 256 | Yan-Yu Lin, Shen-Iuan Liu. 4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation |
| 257 | -- | 261 | Byoungho Kim, Jacob A. Abraham. Capacitor-Coupled Built-Off Self-Test in Analog and Mixed-Signal Embedded Systems |
| 262 | -- | 266 | Terry N. Guo. Unique Measurement and Modeling of Total Phase Noise in RF Receiver |
| 267 | -- | 271 | Fei Xiao. Direct Synthesis Technique for Dual-Passband Filters: Superposition Approach |
| 272 | -- | 276 | Xi Chen, Guanghui He, Jun Ma. VLSI Implementation of a High-Throughput Iterative Fixed-Complexity Sphere Decoder |
| 277 | -- | 281 | Sangmin Kim, Gerald E. Sobelman. Scaling, Offset, and Balancing Techniques in FFT-Based BP Nonbinary LDPC Decoders |
| 282 | -- | 286 | Doru-Florin Chiper. A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture |
| 287 | -- | 291 | Shen-Fu Hsiao, Jun-Hong Zhang Jian, Ming-Chih Chen. Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation |
| 292 | -- | 296 | Yao Chen, Wenwu Yu, Fangfei Li, Shasha Feng. Synchronization of Complex Networks With Impulsive Control and Disconnected Topology |