Journal: IEEE Trans. on Circuits and Systems

Volume 62-I, Issue 10

2369 -- 2379Muhammad Ahmadi, Won Namgoong. Comparator Power Minimization Analysis for SAR ADC Using Multiple Comparators
2380 -- 2390Omar Abdelfattah, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih. An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range
2391 -- 2400Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Herve Naudet. Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique
2401 -- 2410Kun Zhou, Diyi Chen, Xu Zhang, Rui Zhou, Herbert Ho-Ching Iu. Fractional-Order Three-Dimensional $\nabla\times n$ Circuit Network
2411 -- 2422Jung-Mao Lin, Ching-Yuan Yang. A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment
2423 -- 2433Thomas Charisoulis, Douglas Frey, Miltiadis K. Hatalis. Current Feedback Compensation Circuit for 2T1C LED Displays: Method
2434 -- 2444Li Lu, Bozorgmehr Vosooghi, Liang Dai, Changzhi Li. A 0.7 V Relative Temperature Sensor With a Non-Calibrated $\pm 1~^{\circ}{\rm C}$ 3$\sigma$ Relative Inaccuracy
2445 -- 2453Yu-Te Liao, Shih-Chieh Huang, Fuyuan Cheng, Tsung-Heng Tsai. A Fully-Integrated Wireless Bondwire Accelerometer With Closed-loop Readout Architecture
2454 -- 2464Gennady A. Leonov, Nikolay V. Kuznetsov, Marat V. Yuldashev, Renat V. Yuldashev. Hold-In, Pull-In, and Lock-In Ranges of PLL Circuits: Rigorous Mathematical Definitions and Limitations of Classical Theory
2465 -- 2475Wasim Hussain, Yves Blaquière, Yvon Savaria. An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks
2476 -- 2484Alfio Dario Grasso, Gaetano Palumbo, Salvatore Pennisi. High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads
2485 -- 2494Javier Agustin, Marisa López-Vallejo. An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle
2495 -- 2503Young-Ju Kim 0001, Sang-Hye Chung, Kyung-Soo Ha, Seung-Jun Bae, Lee-Sup Kim. A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator
2504 -- 2511Suhas Illath Veetil, Mohamed Helaoui. Discrete Implementation and Linearization of a New Polar Modulator-Based Mixerless Wireless Transmitter Suitable for High Reconfigurability
2512 -- 2522Wei-cheng Sun, Wei-Hsuan Wu, Chia-Hsiang Yang, Yeong-Luh Ueng. An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems
2523 -- 2532Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee. Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture
2533 -- 2543Wanxin Ye, Kaixue Ma, Kiat Seng Yeo, Qiong Zou. A 65 nm CMOS Power Amplifier With Peak PAE above 18.9% From 57 to 66 GHz Using Synthesized Transformer-Based Matching Network
2544 -- 2554Jingyi Wang, Chen Xu, Jianwen Feng, Michael Z. Q. Chen, Xiaofan Wang, Yi Zhao. Synchronization in Moving Pulse-Coupled Oscillator Networks
2555 -- 2564Ning He, Dawei Shi. Event-Based Robust Sampled-Data Model Predictive Control: A Non-Monotonic Lyapunov Function Approach
2565 -- 2573Kai-Yu Hu, Shih-Mei Lin, Chien-Hung Tsai. A Fixed-Frequency Quasi-${\rm V}^{2}$ Hysteretic Buck Converter With PLL-Based Two-Stage Adaptive Window Control
2574 -- 2583Elisenda Bou-Balust, Aiguo Patrick Hu, Eduard Alarcón. Scalability Analysis of SIMO Non-Radiative Resonant Wireless Power Transfer Systems Based on Circuit Models
2584 -- 2593Zhangming Zhu, Yongyuan Li. A Floating Buck Controlled Multi-Mode Dimmable LED Driver Using a Stacked NMOS Switch
2594 -- 2605Wen-Liang Hsue, Wei-Ching Chang. Real Discrete Fractional Fourier, Hartley, Generalized Fourier and Generalized Hartley Transforms With Many Parameters
2606 -- 2616Fernando Chierchie, Sven Ole Aase. Volterra Models for Digital PWM and Their Inverses
2617 -- 2625Robert Rieger. Signal-Folding for Range-Enhanced Acquisition and Reconstruction