| 1 | -- | 9 | Kin Keung Lee, Tor Sverre Lande, Philipp Dominik Häfliger. A Sub-µW Bandgap Reference Circuit With an Inherent Curvature-Compensation Property |
| 10 | -- | 18 | Yung-Hui Chung, Meng-Hsuan Wu, Hung-Sung Li. A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS |
| 19 | -- | 28 | Haoran Yu, Kamal El-Sankary, Ezz I. El-Masry. Distortion Analysis Using Volterra Series and Linearization Technique of Nano-Scale Bulk-Driven CMOS RF Amplifier |
| 29 | -- | 38 | Dong Wu, Cencen Gao, Hui Liu, Nan Xie. A Low Power Double-Sampling Extended Counting ADC With Class-AB OTA for Sensor Arrays |
| 39 | -- | 48 | Behnam Sedighi, Xiaobo Sharon Hu, Huichu Liu, Joseph J. Nahas, Michael T. Niemier. Analog Circuit Design Using Tunnel-FETs |
| 49 | -- | 58 | John A. McNeill, Rabeeh Majidi, Jianping Gong. "Split ADC" Background Linearization of VCO-Based ADCs |
| 59 | -- | 69 | Chao-Chang Chiu, Po-Hsien Huang, Moris Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chao-Cheng Lee. A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement |
| 70 | -- | 79 | Jin-Yi Lin, Chih-Cheng Hsieh. A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS |
| 80 | -- | 89 | Inhee Lee, Gunhee Han, Youngcheol Chae. A 2 mW, 50 dB DR, 10 MHz BW 5 × Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF |
| 90 | -- | 99 | Chun-Wei Hsu, Karthik Tripurari, Shih-An Yu, Peter R. Kinget. A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference |
| 100 | -- | 109 | Jaehyuk Choi, Jungsoon Shin, Byongmin Kang. An Architecture With Pipelined Background Suppression and In-Situ Noise Cancelling for 2D/3D CMOS Image Sensor |
| 110 | -- | 119 | Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao. High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations |
| 120 | -- | 129 | Chao Sun, Asuka Arakawa, Ken Takeuchi. SEA-SSD: A Storage Engine Assisted SSD With Application-Coupled Simulation Platform |
| 130 | -- | 138 | Nerhun Yildiz, Evren Cesur, Kamer Kayaer, Vedat Tavsanoglu, Murathan Alpay. Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator |
| 139 | -- | 148 | Chao Wang, Jun Zhou, Roshan Weerasekera, Bin Zhao, Xin Liu, Philippe Royannez, Minkyu Je. BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems |
| 149 | -- | 156 | Moshe Avital, Hadar Dagan, Itamar Levi, Osnat Keren, Alexander Fish. DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes |
| 157 | -- | 166 | Donald Donglong Chen, Nele Mentens, Frederik Vercauteren, Sujoy Sinha Roy, Ray C. C. Cheung, Derek Pao, Ingrid Verbauwhede. High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems |
| 167 | -- | 176 | Hisato Fujisaka, Takeshi Kamio, Chang-Jun Ahn, Masahiro Sakamoto, Kazuhisa Haeiwa. A Sigma-Delta Domain Lowpass Wave Filter |
| 177 | -- | 184 | Jesus Omar Lacruz, Francisco Garcia-Herrero, Javier Valls-Coquillat, David Declercq. One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes |
| 185 | -- | 194 | Kang-Yi Fan, Pei-Yun Tsai. An RLS Tracking and Iterative Detection Engine for Mobile MIMO-OFDM Systems |
| 195 | -- | 204 | Aimin Jiang, Hon Keung Kwan, Yanping Zhu, Xiaofeng Liu, Ning Xu, Yibin Tang. Design of Sparse FIR Filters With Joint Optimization of Sparsity and Filter Order |
| 205 | -- | 214 | Gourav Saha, Ramkrishna Pasumarthy, Prathamesh Khatavkar. Towards Analog Memristive Controllers |
| 215 | -- | 223 | Shyam Prasad Adhikari, Hyongsuk Kim, Ram Kaji Budhathoki, Changju Yang, Leon O. Chua. A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses |
| 224 | -- | 233 | Jiajia Chen, Chip-Hong Chang, Feng Feng, Weiao Ding, Jiatao Ding. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System |
| 234 | -- | 243 | Kim B. Ostman, Mikko Englund, Olli Viitala, Mikko Kaltiokallio, Kari Stadius, Kimmo Koli, Jussi Ryynänen. Analysis and Design of N-Path Filter Offset Tuning in a 0.7-2.7-GHz Receiver Front-End |
| 244 | -- | 253 | Soo-Hwan Shin, Soon-Jae Kweon, Seong-Hun Jo, Yong-Chang Choi, Sangyoub Lee, Hyung-Joun Yoo. A 0.7-MHz-10-MHz CT+DT Hybrid Baseband Chain With Improved Passband Flatness for LTE Application |
| 254 | -- | 262 | Ahmed Farouk Aref, Thomas M. Hone, Renato Negra. A Study of the Impact of Delay Mismatch on Linearity of Outphasing Transmitters |
| 263 | -- | 272 | Lammert Duipmans, Remko E. Struiksma, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet. Analysis of the Signal Transfer and Folding in N-Path Filters With a Series Inductance |
| 273 | -- | 282 | Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour. Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers |
| 283 | -- | 291 | Basant Kumar Mohanty. Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications |
| 292 | -- | 301 | Chunshu Li, Min Li, Marian Verhelst, André Bourdoux, Liesbet Van der Perre, Sofie Pollin. On the General Mathematical Framework, Calibration/Compensation Method, and Applications of Non-Ideal Software Defined Harmonics Rejection Transceivers |
| 302 | -- | 310 | Hoang Nguyen, Johnson I. Agbinya, John Devlin. FPGA-Based Implementation of Multiple Modes in Near Field Inductive Communication Using Frequency Splitting and MIMO Configuration |
| 311 | -- | 319 | Yasuhiro Sugimoto, Toru Sai, Kei Watanabe, Mikio Abe. Feedback Loop Analysis and Optimized Compensation Slope of the Current-Mode Buck DC-DC Converter in DCM |
| 320 | -- | 328 | Weiguo Lu, Shuang Lang, Luowei Zhou, Herbert Ho-Ching Iu, Tyrone Fernando. Improvement of Stability and Power Factor in PCM Controlled Boost PFC Converter With Hybrid Dynamic Compensation |
| 329 | -- | 332 | Mohammad Saleh Tavazoei. Comments on "Chaotic Characteristics Analysis and Circuit Implementation for a Fractional-Order System" |
| 333 | -- | 335 | Wan Mariam Wan Muda, Victor Sreeram, Minh B. Ha, Abdul Ghafoor. Comments on "Model-Order Reduction Using Variational Balanced Truncation With Spectral Shaping" |