| 549 | -- | 553 | Mincheol Seo, Hwiseob Lee, Jehyeon Gu, Hyungchul Kim, Junghyun Ham, Wooyeol Choi, Yanghun Yun, Kenneth K. O, Youngoo Yang. High-Efficiency Power Amplifier Using an Active Second-Harmonic Injection Technique Under Optimized Third-Harmonic Termination |
| 554 | -- | 558 | Yong-Hwan Moon, In-Seok Kong, Young-Soo Ryu, Jin-Ku Kang. A 2.2-mW 20-135-MHz False-Lock-Free DLL for Display Interface in 0.15-µm CMOS |
| 559 | -- | 563 | Kuo-Hsing Cheng, Cheng-Liang Hung, Cihun-Siyong Alex Gong, Jen-Chieh Liu, Bo-Qian Jiang, Shi-Yang Sun. A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes |
| 564 | -- | 568 | Chao Chen, Jianhui Wu, Dan Huang, Longxing Shi. A Low-Power 2.4-GHz Receiver Front End With a Lateral Current-Reusing Technique |
| 569 | -- | 573 | Reza Hashemian. Fixator-Norator Pairs Versus Direct Analytical Tools in Performing Analog Circuit Designs |
| 574 | -- | 578 | Fermin Esparza-Alfaro, Salvatore Pennisi, Gaetano Palumbo, Antonio J. López-Martín. Low-Power Class-AB CMOS Voltage Feedback Current Operational Amplifier With Tunable Gain and Bandwidth |
| 579 | -- | 583 | Fan Xie 0002, Bo Zhang, Ru Yang, Dong Yuan Qiu. Quantifying the Complexity of DC-DC Switching Converters by Joint Entropy |
| 584 | -- | 588 | Mohammad Taherzadeh-Sani, Reza Lotfi, Frederic Nabki. A 10-bit 110 kS/s 1.16 µW SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications |
| 589 | -- | 593 | Hesham Omran, Muhammad Arsalan, Khaled N. Salama. 7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter |
| 594 | -- | 598 | Mohammed Abdulaziz, Markus Tormanen, Henrik Sjöland. A Compensation Technique for Two-Stage Differential OTAs |
| 599 | -- | 603 | Dongkyung Park, Hoi Lee. Improvements in Light-Load Efficiency and Operation Frequency for Low-Voltage Current-Mode Integrated Boost Converters |
| 604 | -- | 608 | Aditya Banuaji, Hyouk-Kyu Cha. A 15-V Bidirectional Ultrasound Interface Analog Front-End IC for Medical Imaging Using Standard CMOS Technology |
| 609 | -- | 613 | Alexios Balatsoukas-Stimming, Alexandre J. Raymond, Warren J. Gross, Andreas Burg. Hardware Architecture for List Successive Cancellation Decoding of Polar Codes |
| 614 | -- | 618 | Choon Ki Ahn. ∞ Suppression of Limit Cycles in Interfered Two-Dimensional Digital Filters: A Fornasini-Marchesini Model Case |
| 619 | -- | 623 | Xiaoyan He, Qingyun Wang, Wenwu Yu. Finite-Time Containment Control for Second-Order Multiagent Systems Under Directed Topology |
| 624 | -- | 628 | Reza Hashemian. Extraction of Poles and Zeros of an RC Circuit With Roots on the Real Axis |
| 629 | -- | 633 | Hyun Hee Park, Gyu-Hyeong Cho. A dc-dc Converter for a Fully Integrated PID Compensator With a Single Capacitor |
| 634 | -- | 638 | Zhuochao Sun, Kin Wai Roy Chew, Howard Tang, Guolei Yu, Liter Siek. A 0.42-V Input Boost dc-dc Converter With Pseudo-Digital Pulsewidth Modulation |
| 639 | -- | 0 | Xiao Pu, Ajay Kumar, Krishnaswamy Nagaraj. Corrections to "Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference" |