Journal: IEEE Trans. on Circuits and Systems

Volume 62, Issue 9

2137 -- 2146Apisak Worapishet, Andreas Demosthenous. Generalized Analysis of Random Common-Mode Rejection Performance of CMOS Current Feedback Instrumentation Amplifiers
2147 -- 2155Junan Lee, Himchan Park, Bongsub Song, Kiwoon Kim, Jaeha Eom, Kyunghoon Kim, Jinwook Burm. High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs
2156 -- 2166Yun-Rae Jo, Seong-Kwan Hong, Oh-Kyong Kwon. A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits
2167 -- 2176Zhangming Zhu, Yuhua Liang. A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18- μm CMOS for Medical Implant Devices
2177 -- 2186Ismail Cevik, Suat U. Ay. An Ultra-Low Power Energy Harvesting and Imaging (EHI) Type CMOS APS Imager With Self-Power Capability
2187 -- 2195Robert D'Angelo, Sameer R. Sonkusale. A Time-Mode Translinear Principle for Nonlinear Analog Computation
2196 -- 2206Jianyu Zhong, Yan Zhu 0001, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs
2207 -- 2215Paolo Maffezzoni, Luca Daniel, Nikhil Shukla, Suman Datta, Arijit Raychowdhury. Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators
2216 -- 2226Jiageng Huang, Shiliang Yang, George Jie Yuan. A 75 dB SNDR 10-MHz Signal Bandwidth Gm-C-Based Sigma-Delta Modulator With a Nonlinear Feedback Compensation Technique
2227 -- 2237Congyin Shi, Edgar Sánchez-Sinencio. 150-850 MHz High-Linearity Sine-wave Synthesizer Architecture Based on FIR Filter Approach and SFDR Optimization
2238 -- 2247Marco Cannizzaro, Salomon Beer, Jordi Cortadella, Ran Ginosar, Luciano Lavagno. SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits
2248 -- 2259Thian Fatt Tay, Chip-Hong Chang, L. Sousa. Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS
2260 -- 2267Yaara Neumeier, Y. Pesso, Osnat Keren. Efficient Implementation of Punctured Parallel Finite Field Multipliers
2268 -- 2279Simran Singh, Lauri Anttila, Michael Epp, Wolfgang Schlecker, Mikko Valkama. Frequency Response Mismatches in 4-channel Time-Interleaved ADCs: Analysis, Blind Identification, and Correction
2280 -- 2289Salvatore Caporale, Fabio Pareschi, Valerio Cambareri, Riccardo Rovatti, Gianluca Setti. A Soft-Defined Pulse Width Modulation Approach - Part I: Principles
2290 -- 2300Salvatore Caporale, Fabio Pareschi, Valerio Cambareri, Riccardo Rovatti, Gianluca Setti. A Soft-Defined Pulse Width Modulation Approach - Part II: System Modeling
2301 -- 2311Jingyuan Zhan, Xiang Li. Asynchronous Consensus of Multiple Double-Integrator Agents With Arbitrary Sampling Intervals and Communication Delays
2312 -- 2323Tao Liu, David J. Hill, Jun Zhao 0002. Output Synchronization of Dynamical Networks with Incrementally-Dissipative Nodes and Switching Topology
2324 -- 2333Viki Szortyka, Kuba Raczkowski, Maarten Kuijk, Piet Wambacq. A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers
2334 -- 2341A. Mazzanti, A. Bevilacqua. On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators
2342 -- 2350David Seebacher, Peter Singerl, Christian Schuberth, Franz Dielacher, Y. Papananos, N. Alexiou, K. Galanopoulos, Michael Ernst Gadringer, Wolfgang Bosch. Predistortion of Digital RF PWM Signals Considering Conditional Memory
2351 -- 2360Sujan K. Manohar, L. R. Hunt, Poras T. Balsara, D. K. Bhatia, V. V. Paduvalli. Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter
2361 -- 2363Yongle Wu, Lingxiao Jiao, Yuanan Liu. Comments on "Novel Dual-Band Matching Network for Effective Design of Concurrent Dual-Band Power Amplifiers"

Volume 62, Issue 5

421 -- 425Fahad Quiz, Quoc-Tai Duong, Jerzy Dabrowski. Two-Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering
426 -- 430Manzur Rahman, Arindam Sanyal, Nan Sun. A Novel Hybrid Radix-3/Radix-2 SAR ADC With Fast Convergence and Low Hardware Complexity
431 -- 435Linxiao Zhang, Yang Xu, Karthik Tripurari, Peter R. Kinget, Harish Krishnaswamy. Analysis and Design of a 0.6- to 10.5-GHz LNTA for Wideband Receivers
436 -- 440Jerrin Pathrose, Chengye Liu, Kevin T. C. Chai, Yong Ping Xu. A Time-Domain Band-Gap Temperature Sensor in SOI CMOS for High-Temperature Applications
441 -- 445Geunyeong Park, Minkyu Song. A CMOS Current-Steering D/A Converter With Full-Swing Output Voltage and a Quaternary Driver
446 -- 450Hugo B. Goncalves, Miguel A. Martins, Jorge R. Fernandes. Fully Integrated Energy Harvesting Circuit With -25-dBm Sensitivity Using Transformer Matching
451 -- 455Jong-Boo Kim, Seong-Kwan Hong, Oh-Kyong Kwon. A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method
456 -- 460Kareem Ragab, Long Chen, Arindam Sanyal, Nan Sun. Digital Background Calibration for Pipelined ADCs Based on Comparator Decision Time Quantization
461 -- 465Pi-Feng Chiu, Borivoje Nikolic. A Differential 2R Crosspoint RRAM Array With Zero Standby Current
466 -- 470Shen-Fu Hsiao, Po-Han Wu, Chia-Sheng Wen, Pramod Kumar Meher. Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation
471 -- 475Chia-Hsiang Chen, Shiming Song, Zhengya Zhang. An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation
476 -- 480Mandeep Chaudhary, Peter Lee 0002. An Improved Two-Step Binary Logarithmic Converter for FPGAs
481 -- 485Jiafeng Xie, Pramod Kumar Meher, Zhi-Hong Mao. m) Based on Irreducible Trinomials
486 -- 490Håkan Johansson, Heinz G. Göckler. Two-Stage-Based Polyphase Structures for Arbitrary-Integer Sampling Rate Conversion
491 -- 495Rajib Lochan Das, Mrityunjoy Chakraborty. On Convergence of Proportionate-Type Normalized Least Mean Square Algorithms
496 -- 500Yun Huang, Peng Zhang, Weifeng Zhao. Novel Grid Multiwing Butterfly Chaotic Attractors and Their Circuit Design
501 -- 505Matteo Biggio, Alberto Oliveri, Flavio Stellino, Mauro Parodi, Marco Storace. A Circuit Model of Hysteresis and Creep
506 -- 510Ines Zaidi, Mohamed Chaabane, Fernando Tadeo, Abdellah Benzaouia. Static State-Feedback Controller and Observer Design for Interval Positive Systems With Time Delay
511 -- 515Yao Chen. Characterizing the Convergence of a Distributed Consensus Algorithm via Relative Hull