| 431 | -- | 461 | JoAnn M. Paul, Donald E. Thomas, Andrew S. Cassidy. High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors |
| 462 | -- | 491 | Arnab Roy, S. K. Panda, Rajeev Kumar, P. P. Chakrabarti. A framework for systematic validation and debugging of pipeline simulators |
| 492 | -- | 522 | Ansuman Banerjee, Pallab Dasgupta. The open family of temporal logics: Annotating temporal operators with input constraints |
| 523 | -- | 545 | Farinaz Koushanfar, Inki Hong, Miodrag Potkonjak. Behavioral synthesis techniques for intellectual property protection |
| 546 | -- | 560 | Puneet Gupta, Andrew B. Kahng, Stefanus Mantik. Routing-aware scan chain ordering |
| 561 | -- | 572 | Hua Xiang, Xiaoping Tang, Martin D. F. Wong. An algorithm for integrated pin assignment and buffer planning |
| 573 | -- | 586 | Jaehwan John Lee, Vincent John Mooney III. An ::::o::::(::::min::::(::::m::::, ::::n::::)) parallel deadlock detection algorithm |