| 187 | -- | 204 | Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria. Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques |
| 205 | -- | 228 | Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy. Synthesis of skewed logic circuits |
| 229 | -- | 257 | Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen. Optimizing instruction TLB energy using software and hardware techniques |
| 258 | -- | 278 | Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran. Efficient techniques for transition testing |
| 279 | -- | 302 | Kara K. W. Poon, Steven J. E. Wilton, Andy Yan. A detailed power model for field-programmable gate arrays |
| 303 | -- | 329 | Soumendu Bhattacharya, Abhijit Chatterjee. Optimized wafer-probe and assembled package test design for analog circuits |
| 330 | -- | 353 | Saraju P. Mohanty, N. Ranganathan. Energy-efficient datapath scheduling using multiple voltages and dynamic clocking |
| 354 | -- | 368 | Azadeh Davoodi, Ankur Srivastava. Voltage scheduling under unpredictabilities: a risk management paradigm |
| 369 | -- | 388 | Zhong Wang, Xiaobo Sharon Hu. Energy-aware variable partitioning and instruction scheduling for multibank memory architectures |
| 389 | -- | 430 | Jason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan. Large-scale circuit placement |