Journal: ACM Trans. Design Autom. Electr. Syst.

Volume 10, Issue 4

587 -- 588Ian G. Harris. Introduction
589 -- 609Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner. XFM: An incremental methodology for developing formal models
610 -- 626Masahiro Fujita. Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths
627 -- 650Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Chih-Chan Lin. Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
651 -- 672Jason T. Higgins, Mark Aagaard. Simplifying the design and automating the verification of pipelines with structural hazards
673 -- 689Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi. Instruction-level test methodology for CPU core self-testing
690 -- 701Ahmad A. Al-Yamani, Edward J. McCluskey. Test chip experimental results on high-level structural test
702 -- 723Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, Jef L. van Meerbergen. An event-based monitoring service for networks on chip