| 0 | -- | 0 | Parag K. Lala. Guest Editorial |
| 313 | -- | 331 | Mark G. Karpovsky. Integrated On-Line and Off-Line Error Detection Mechanisms in the Coding Theory Framework |
| 321 | -- | 336 | François Verdier, Bertrand Zavidovique. A High Level Synthesis System for VLSI Image Processing Applications |
| 333 | -- | 345 | A. Morosow, V. V. Saposhnikov, Vl. V. Saposhnikov, Michael Gössel. Self-Checking Combinational Circuits with Unidirectionally Independent Outputs |
| 337 | -- | 346 | Chittaranjan A. Mandal, Partha Pratim Chakrabarti, Sujoy Ghose. Complexity of Scheduling in High Level Synthesis |
| 347 | -- | 356 | Steffen Tarnick. Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability |
| 347 | -- | 352 | C. P. Ravikumar, Nikhil Sharma. Testability-Driven Layout of Combinational Circuits |
| 353 | -- | 364 | Sudip Nag, Kaushik Roy 0001. Performance and Wirability Driven Layout for Row-Based FPGAs |
| 357 | -- | 372 | Yeong-Ruey Shieh, Cheng-Wen Wu. Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults |
| 365 | -- | 383 | Teofilo F. Gonzalez, Si-Qing Zheng. On Ensuring Multilayer Wirability by Stretching Layouts |
| 373 | -- | 383 | Jien-Chung Lo. A Case Study of Self-Checking Circuits Reliability |
| 385 | -- | 399 | Ray-I Chang, Pei-Yung Hsiao. Macro-Cell Placement for Custom-Chip Design Using Self-Organizing Fuzzy Technique |
| 385 | -- | 392 | Feodor S. Vainstein. Self Checking Design Technique for Numerical Computations |
| 401 | -- | 423 | Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni. Formal Codesign Methodology with Multistep Partitioning |
| 425 | -- | 436 | Dinesh P. Mehta. CLOTH MEASURE: A Software Tool for Estimating the Memory Requirements of Corner Stitching Data Structures |