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    Journal: VLSI Design

    Volume 1999, Issue 3

    0 -- 0Azzedine Boukerche. Guest Editorial
    219 -- 235Jörg Keller 0001, Thomas Rauber, Bernd Rederlechner. Scalability Analysis for Conservative Simulation of Logical Circuits
    237 -- 251Raghunandan Rajan, Radharamanan Radhakrishnan, Philip A. Wilsey. Dynamic Cancellation: Selecting Time Warp Cancellation Strategies at Runtime
    253 -- 270Hong K. Kim, Jack S. N. Jean. Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation
    271 -- 290Falguni Sarkar, Sajal K. Das. Design and Implementation of Dynamic Load Balancing Algorithms for Rollback Reduction in Optimistic PDES
    291 -- 313Hervé Avril, Carl Tropper. Scalable Clustered Time Warp and Logic Simulation
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