Journal: VLSI Design

Volume 1999, Issue 4

0 -- 0Carl L. Gardner. Guest Editorial
315 -- 323Philippe Bechouche. Semi-classical Limit in a Semiconductor Superlattice
325 -- 338Matthias Ehrhardt. Discrete Transparent Boundary Conditions for General Schrödinger-type Equations
339 -- 350Florian Frommlet, Peter A. Markowich, Christian A. Ringhofer. A Wignerfunction Approach to Phonon Scattering
351 -- 355Carl L. Gardner. Theory and Simulation of the Smooth Quantum Hydrodynamic Model
357 -- 364I. Gasser. On Hartree-Fock Systems
365 -- 375I. Gasser, Peter A. Markowich, Benoit Perthame. Dispersion Lemmas Revisited
377 -- 383Terry Gough, Reinhard Illner. Modeling Crystallization Dynamics when the Avrami Model Fails
385 -- 396Horst Lange, Bruce Toomire, Paul F. Zweifel. Inflow Boundary Conditions in Quantum Transport Theory
397 -- 413Peter A. Markowich, Paola Pietra, Carsten Pohl. Semiclassical Analysis of Discretizations of Schrödinger-type Equations
415 -- 426Norbert J. Mauser. Rigorous Derivation of the Pauli Equation With Time-dependent Electromagnetic Field
427 -- 434Paola Pietra, Carsten Pohl. Weak Limits of the Quantum Hydrodynamic Model
435 -- 0. Erratum

Volume 1999, Issue 3

0 -- 0Azzedine Boukerche. Guest Editorial
219 -- 235Jörg Keller 0001, Thomas Rauber, Bernd Rederlechner. Scalability Analysis for Conservative Simulation of Logical Circuits
237 -- 251Raghunandan Rajan, Radharamanan Radhakrishnan, Philip A. Wilsey. Dynamic Cancellation: Selecting Time Warp Cancellation Strategies at Runtime
253 -- 270Hong K. Kim, Jack S. N. Jean. Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation
271 -- 290Falguni Sarkar, Sajal K. Das. Design and Implementation of Dynamic Load Balancing Algorithms for Rollback Reduction in Optimistic PDES
291 -- 313Hervé Avril, Carl Tropper. Scalable Clustered Time Warp and Logic Simulation

Volume 1999, Issue 2

105 -- 117Mukkai S. Krishnamoorthy, James Loy, John F. McDonald. Optimal Differential Routing based on Finite State Machine Theory
119 -- 133Ali Najafi, Behrouz Farhang-Boroujeny, Ganesh S. Samudra. A VLSI Design for Implementation of Transform Domain Adaptive Filters
127 -- 141Albrecht P. Stroele. Signature Analysis for Test Responses of Sequential Circuits
135 -- 146Bogdan J. Falkowski, Chip-Hong Chang. An Efficient Algorithm for the Calculation of Generalized Adding and Arithmetic Transforms From Disjoint Cubes of Boolean Functions
143 -- 153Wen-Jer Wu, Chuan Yi Tang. Automatic Test Timing Assignment for RAMs Using Linear Programming
147 -- 157Georgios Theodoridis, Spyros Theoharis, Dimitrios Soudris, Constantinos E. Goutis. A New Method for Low Power Design of Two-Level Logic Circuits
155 -- 167Jin-Tai Yan. T-type Junction Region
159 -- 180Jong-Tae Kim, Fadi J. Kurdahi, Nohbyung Park. System-level Time-stationary Control Synthesis for Pipelined Data Paths
169 -- 176Jin-Tai Yan. An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement
177 -- 202Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis. Computation Reordering: A Novel Transformation for Low Power DSP Synthesis
181 -- 201Phillip Baraona, Perry Alexander. Abstract Architecture Representation Using VSPEC
203 -- 211A. Srivastava. Influence of BJT Transit Frequency Limit Relation to MOSFET Parameters on the Switching Speed of BiCMOS Digital Circuits
203 -- 215Lizy Kurian John. Memory Chips with Adjustable Configurations
213 -- 218S. E.-D. Habib, G. J. Al-Karim. An Initialization Technique for the Waveform-Relaxation Circuit Simulation
217 -- 235Peter J. Ashenden, Philip A. Wilsey. Principles for Language Extensions to VHDL to Support High-Level Modeling
237 -- 247Edward Y. C. Cheng, Sartaj Sahni. A Fast Algorithm for Performance-Driven Module Implementation Selection

Volume 1999, Issue 1

0 -- 0Jun Dong Cho. Preface
0 -- 0Stephan Olariu, Rong Lin. Guest Editorial
1 -- 20Dirk Stroobandt, Jan Van Campenhout. Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle
1 -- 16Ten-Hwang Lai, Ming-Jye Sheng. Sorting on Reconfigurable Meshes: An Irregular Decomposition Approach
17 -- 28Yosi Ben-Asher, Assaf Schuster. Single Step Undirected Reconfigurable Networks
21 -- 34Andrew B. Kahng, Sudhakar Muddu, Egino Sarto. Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs
29 -- 54Sotirios G. Ziavras. Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing
35 -- 55Malgorzata Chrzanowska-Jeske, Yang Xu, Marek A. Perkowski. Logic Synthesis for a Regular Layout
55 -- 67Hsiu-Niang Chen, Kuo-Liang Chung. Partitionable Bus-based String-matching Algorithm for Run-length Coded Strings With VLDCs
57 -- 70Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh. Placement with Incomplete Data
69 -- 81Martin Middendorf, Hartmut Schmeck, Heiko Schröder, Gavin Turner. Multiplication of Matrices With Different Sparseness Properties on Dynamically Reconfigurable Meshes
71 -- 86Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng. Empirical Study of Block Placement by Cluster Refinement
83 -- 90Rong Lin, Stephan Olariu. Reconfigurable Shift Switching Parallel Comparators
87 -- 97S.-H. Nam, J. D. Cho, D. Wagner. Lower-Power and Min-Crosstalk Channel Routing for Deep-Submicron Layout Design
91 -- 104Joon Shik Lim, S. Sitharama Iyengar, Si-Qing Zheng. 1 and Link Metric Shortest Paths in the Presence of Orthogonal Obstacles: A Heuristic Approach
99 -- 116Charles J. Alpert, Andrew E. Caldwell, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, M. S. Moroz. Analytical Engines are Unnecessary in Top-down Partitioning-based Placement
117 -- 125Wonjong Kim, Hyunchul Shin. Hierarchy Restructuring for Hierarchical LVS Comparison