0 | -- | 0 | Jun Dong Cho. Preface |
0 | -- | 0 | Stephan Olariu, Rong Lin. Guest Editorial |
1 | -- | 20 | Dirk Stroobandt, Jan Van Campenhout. Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle |
1 | -- | 16 | Ten-Hwang Lai, Ming-Jye Sheng. Sorting on Reconfigurable Meshes: An Irregular Decomposition Approach |
17 | -- | 28 | Yosi Ben-Asher, Assaf Schuster. Single Step Undirected Reconfigurable Networks |
21 | -- | 34 | Andrew B. Kahng, Sudhakar Muddu, Egino Sarto. Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs |
29 | -- | 54 | Sotirios G. Ziavras. Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing |
35 | -- | 55 | Malgorzata Chrzanowska-Jeske, Yang Xu, Marek A. Perkowski. Logic Synthesis for a Regular Layout |
55 | -- | 67 | Hsiu-Niang Chen, Kuo-Liang Chung. Partitionable Bus-based String-matching Algorithm for Run-length Coded Strings With VLDCs |
57 | -- | 70 | Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh. Placement with Incomplete Data |
69 | -- | 81 | Martin Middendorf, Hartmut Schmeck, Heiko Schröder, Gavin Turner. Multiplication of Matrices With Different Sparseness Properties on Dynamically Reconfigurable Meshes |
71 | -- | 86 | Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng. Empirical Study of Block Placement by Cluster Refinement |
83 | -- | 90 | Rong Lin, Stephan Olariu. Reconfigurable Shift Switching Parallel Comparators |
87 | -- | 97 | S.-H. Nam, J. D. Cho, D. Wagner. Lower-Power and Min-Crosstalk Channel Routing for Deep-Submicron Layout Design |
91 | -- | 104 | Joon Shik Lim, S. Sitharama Iyengar, Si-Qing Zheng. 1 and Link Metric Shortest Paths in the Presence of Orthogonal Obstacles: A Heuristic Approach |
99 | -- | 116 | Charles J. Alpert, Andrew E. Caldwell, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, M. S. Moroz. Analytical Engines are Unnecessary in Top-down Partitioning-based Placement |
117 | -- | 125 | Wonjong Kim, Hyunchul Shin. Hierarchy Restructuring for Hierarchical LVS Comparison |