Journal: VLSI Design

Volume 2, Issue 4

0 -- 0Pradip K. Srimani. Guest Editor's Introduction
287 -- 303Susan R. Dickey, Richard Kenner. Design of Components for a Low Cost Combining Switch
305 -- 314Peter W. Thompson, Julian D. Lewis. The STC104 Packet Routing Chip
315 -- 333Kazuhiro Aoyama, Andrew A. Chien. The Cost of Adaptivity and Virtual Lanes in a Wormhole Router
335 -- 351Sajal K. Das 0001, Sabine R. Öhring, Amit K. Banerjee. Embeddings into Hyper Petersen Networks: Yet Another Hypercube-Like Interconnection Topology
353 -- 364Isaac D. Scherson, Chi-Kai Chien. Least Common Ancestor Networks
365 -- 374S. Q. Zheng 0001, Bin Cong, Saïd Bettayeb. Trade-Off Considerations in Designing Efficient VLSI Feasible Interconnection Networks
375 -- 388M. T. Raghunath, Abhiram Ranade. Designing Interconnection Networks for Multi-level Packaging
389 -- 396Ke Qiu, Selim G. Akl. On Some Properties of the Star Graph