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    Journal: VLSI Design

    Volume 2, Issue 4

    0 -- 0Pradip K. Srimani. Guest Editor's Introduction
    287 -- 303Susan R. Dickey, Richard Kenner. Design of Components for a Low Cost Combining Switch
    305 -- 314Peter W. Thompson, Julian D. Lewis. The STC104 Packet Routing Chip
    315 -- 333Kazuhiro Aoyama, Andrew A. Chien. The Cost of Adaptivity and Virtual Lanes in a Wormhole Router
    335 -- 351Sajal K. Das 0001, Sabine R. Öhring, Amit K. Banerjee. Embeddings into Hyper Petersen Networks: Yet Another Hypercube-Like Interconnection Topology
    353 -- 364Isaac D. Scherson, Chi-Kai Chien. Least Common Ancestor Networks
    365 -- 374S. Q. Zheng 0001, Bin Cong, Saïd Bettayeb. Trade-Off Considerations in Designing Efficient VLSI Feasible Interconnection Networks
    375 -- 388M. T. Raghunath, Abhiram Ranade. Designing Interconnection Networks for Multi-level Packaging
    389 -- 396Ke Qiu, Selim G. Akl. On Some Properties of the Star Graph

    Volume 2, Issue 3

    185 -- 198Chien-In Henry Chen. Partitioning Techniques for Built-In Self-Test Design
    199 -- 207Hyung Ki Lee, Dong S. Ha 0001. An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits
    209 -- 221Fadi Busaba, Parag K. Lala. Techniques for Self-Checking Combinational Logic Synthesis
    223 -- 231Hassan Farhat, Steven G. From. A Quadratic Programming Approach to Estimating the Testability and Random or Deterministic Coverage of a VLSl Circuit
    233 -- 239C. P. Ravikumar, Haroon Rasheed. TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing
    241 -- 257Chi-Yu Mao, Yu Hen Hu. SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm
    259 -- 265Ausif Mahmood, Jayantha Herath, J. Jayasumana. An Improved Data Flow Architecture for Logic Simulation Acceleration
    267 -- 286Ali R. Hurson, Simin H. Pakzad. Modular Scheme for Designing Special Purpose Associative Memories and Beyond

    Volume 2, Issue 2

    0 -- 0Si-Qing Zheng, Dian Zhou. Preface
    89 -- 103Kuo-Hua Wang, Cheng Chen, Ting Ting Hwang. Technology Mapping for FPGA Using Generalized Functional Decomposition
    105 -- 116Subbu Muddappa, Rafic Z. Makki, Zbigniew Michalewicz, Sridhar Isukapalli. Pioneer: A New Tool for Coding of Multi-Level Finite State Machines Based on Evolution Programming
    117 -- 129Youssef Saab, Cheng-Hua Chen. An Effective Solution to the Linear Placement Problem
    131 -- 141Wenjun Zhuang, Yong Ching Lim, Ganesh Samudra, Neng Yan. A New Clustering Method Based on General Connectivity
    143 -- 156Cheng-Hsi Chen, Ioannis G. Tollis. Area Optimization of Slicing Floorplans in Parallel
    157 -- 169Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh. On the Minimum Density Interconnection Tree Problem
    171 -- 183Yang Cai 0003, D. F. Wong 0001, Jason Cong. Channel Density Minimization by Pin Permutation

    Volume 2, Issue 1

    1 -- 16Peter J. Ashenden, Henry Detmold, Wayne S. McKeen. Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms
    17 -- 32Nohbyung Park, Fadi J. Kurdahi. Register-Transfer Synthesis of Pipelined Data Paths
    33 -- 50Andrzej Sobski, Alexander Albicki. High Throughput Error Control Using Parallel CRC
    51 -- 68Spyros Tragoudas. On Channel Routing Problems With Interchangeable Terminals
    69 -- 80Anand V. Hudli, Raghu V. Hudli. Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits
    81 -- 88Rafic Z. Makki, Shyang-Tai Su. Analysis and Characterization of State Assignment Techniques for Sequential Machines
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