Journal: VLSI Design

Volume 2, Issue 1

1 -- 16Peter J. Ashenden, Henry Detmold, Wayne S. McKeen. Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms
17 -- 32Nohbyung Park, Fadi J. Kurdahi. Register-Transfer Synthesis of Pipelined Data Paths
33 -- 50Andrzej Sobski, Alexander Albicki. High Throughput Error Control Using Parallel CRC
51 -- 68Spyros Tragoudas. On Channel Routing Problems With Interchangeable Terminals
69 -- 80Anand V. Hudli, Raghu V. Hudli. Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits
81 -- 88Rafic Z. Makki, Shyang-Tai Su. Analysis and Characterization of State Assignment Techniques for Sequential Machines