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Journal: VLSI Design
Home
Index
Info
Issue
Volume
2
, Issue
1
1
--
16
Peter J. Ashenden
,
Henry Detmold
,
Wayne S. McKeen
.
Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms
17
--
32
Nohbyung Park
,
Fadi J. Kurdahi
.
Register-Transfer Synthesis of Pipelined Data Paths
33
--
50
Andrzej Sobski
,
Alexander Albicki
.
High Throughput Error Control Using Parallel CRC
51
--
68
Spyros Tragoudas
.
On Channel Routing Problems With Interchangeable Terminals
69
--
80
Anand V. Hudli
,
Raghu V. Hudli
.
Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits
81
--
88
Rafic Z. Makki
,
Shyang-Tai Su
.
Analysis and Characterization of State Assignment Techniques for Sequential Machines