External Links

    Journal: VLSI Design

    Volume 2, Issue 3

    185 -- 198Chien-In Henry Chen. Partitioning Techniques for Built-In Self-Test Design
    199 -- 207Hyung Ki Lee, Dong S. Ha 0001. An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits
    209 -- 221Fadi Busaba, Parag K. Lala. Techniques for Self-Checking Combinational Logic Synthesis
    223 -- 231Hassan Farhat, Steven G. From. A Quadratic Programming Approach to Estimating the Testability and Random or Deterministic Coverage of a VLSl Circuit
    233 -- 239C. P. Ravikumar, Haroon Rasheed. TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing
    241 -- 257Chi-Yu Mao, Yu Hen Hu. SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm
    259 -- 265Ausif Mahmood, Jayantha Herath, J. Jayasumana. An Improved Data Flow Architecture for Logic Simulation Acceleration
    267 -- 286Ali R. Hurson, Simin H. Pakzad. Modular Scheme for Designing Special Purpose Associative Memories and Beyond
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