| 1 | -- | 10 | Dinesh Bhatia, Amit Chowdhary. A Multi-Terminal Net Router for Field-Programmable Gate Arrays |
| 11 | -- | 16 | Jin-Tai Yan, Pei-Yung Hsiao. An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment |
| 17 | -- | 32 | Pei-Yung Hsiao. Nearly Balanced Quad List Quad Tree -A Data Structure for VLSI Layout Systems |
| 33 | -- | 40 | Dharmavani Bhagavathi, Himabindu Gurla, Stephan Olariu, James L. Schwing, Jingyuan Zhang. Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs |
| 41 | -- | 51 | Jai-Shen Huang, Yeh-Hao Chin. An Efficient Algorithm for the Split K-Layer Circular Topological Via Minimization Problem |
| 53 | -- | 57 | Sunil Chopra, Kalyan T. Talluri. Minimum-Cost Node-Disjoint Steiner Trees in Series-Parallel Networks |
| 59 | -- | 68 | Ausif Mahmood. Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures |
| 69 | -- | 74 | A. Srivastava, S. R. Palavali. Integration of SPICE with TEK LV500 ASIC Design Verification System |
| 75 | -- | 81 | A. Srivastava, K. Venkatapathy. Design and Implementation of a Low Power Ternary Full Adder |
| 83 | -- | 90 | B. Majumdar, V. V. Ramakrishna, P. S. Dey, A. K. Majumdar. Design of an ASIC Chip for Skeletonization of Graylevel Digital Images |