| 0 | -- | 0 | Sunil R. Das. Guest Editorial |
| 149 | -- | 165 | Wen-Ben Jone, Nigam Shah, Anita Gleason, Sunil R. Das. PGEN: A Novel Approach to Sequential Circuit Test Generation |
| 167 | -- | 179 | Ananta K. Majhi, James Jacob, Lalit M. Patnaik. A Novel Path Delay Fault Simulator Using Binary Logic |
| 181 | -- | 197 | Kyuchull Kim, Kewal K. Saluja. HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits |
| 199 | -- | 205 | Geetani Edirisooriya. Closed Form Aliasing Probability For Q-ary Symmetric Errors |
| 207 | -- | 215 | M. Srinivas, L. M. Patnaik. On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach |
| 217 | -- | 229 | Evstratios Vandris, Gerald E. Sobelman. Switch-level Differential Fault Simulation of MOS VLSI Circuits |
| 231 | -- | 242 | Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana. Fault Modeling of ECL for High Fault Coverage of Physical Defects |
| 243 | -- | 256 | Anupam Basu, Dilip K. Banerji, Amit Basu, Thomas Charles Wilson, Jayanti C. Majithia. A Modified Approach to Test Plan Generation for Combinational Logic Blocks |
| 257 | -- | 269 | Subir Bandyopadhyay, Abhijit Sengupta, Bhargab B. Bhattacharya. A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays |
| 271 | -- | 274 | . Erratum |