External Links

    Journal: VLSI Design

    Volume 4, Issue 2

    0 -- 0Ausif Mahmood. Hardware Accelerators for VLSI Design
    91 -- 105Ausif Mahmood, William I. Baker. An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations
    107 -- 118E. Scott Fehr, Stephen A. Szygenda, Granville E. Ott. An Integrated Hardware Array for Very High Speed Logic Simulation
    119 -- 133Sungho Kang, Youngmin Hur, Stephen A. Szygenda. A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture
    135 -- 139Neil J. Howard, Andrew M. Tyrrell, Nigel M. Allinson. The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks
    141 -- 147Seokjin Kim, Ramalingam Sridhar. Hardware Design Rule Checker Using a CAM Architecture
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