| 195 | -- | 217 | Virginio Cantoni, V. Gesu, Marco Ferretti, Stefano Levialdi, Roberto M. Negrini, Renato Stefanelli. The PAPIA system |
| 219 | -- | 233 | Richard C. North, Walter H. Ku. beta-bit serial/parallel multipliers |
| 235 | -- | 252 | Wayne P. Burleson, Louis L. Scharf. A VLSI design methodology for distributed arithmetic |
| 253 | -- | 269 | Vijay K. Jain, David L. Landis, David C. Keezer, K. T. Wilson, D. Whittaker. Wafer Scale Integration: A university perspective |
| 271 | -- | 285 | R. M. Lea. WASP: A WSI Associative String Processor |
| 287 | -- | 299 | Marios D. Dikaiakos, Kenneth Steiglitz. Comparison of tree and straight-line clocking for long systolic arrays |
| 301 | -- | 311 | Ron Bourassa, Tim Coffman, Joe Brewer. Ultra large scale static rams |
| 313 | -- | 324 | Poras T. Balsara, Mary Jane Irwin. Image processing on a memory array architecture |