External Links

    Journal: VLSI Signal Processing

    Volume 2, Issue 4

    195 -- 217Virginio Cantoni, V. Gesu, Marco Ferretti, Stefano Levialdi, Roberto M. Negrini, Renato Stefanelli. The PAPIA system
    219 -- 233Richard C. North, Walter H. Ku. beta-bit serial/parallel multipliers
    235 -- 252Wayne P. Burleson, Louis L. Scharf. A VLSI design methodology for distributed arithmetic
    253 -- 269Vijay K. Jain, David L. Landis, David C. Keezer, K. T. Wilson, D. Whittaker. Wafer Scale Integration: A university perspective
    271 -- 285R. M. Lea. WASP: A WSI Associative String Processor
    287 -- 299Marios D. Dikaiakos, Kenneth Steiglitz. Comparison of tree and straight-line clocking for long systolic arrays
    301 -- 311Ron Bourassa, Tim Coffman, Joe Brewer. Ultra large scale static rams
    313 -- 324Poras T. Balsara, Mary Jane Irwin. Image processing on a memory array architecture

    Volume 2, Issue 3

    131 -- 137Graham A. Jullien, Subir Bandyopadhyay, William C. Miller, M. Taheri. A low-overhead scheme for testing a bit-level finite ring systolic array
    139 -- 148Mark R. Greenstreet, Kenneth Steiglitz. Bubbles can make self-timed pipelines fast
    149 -- 158M. Yan, John V. McCanny. A bit-level systolic architecture for implementing a VQ tree search
    159 -- 172Thomas L. Wernimont, David K. Hwang, W. Kent Fuchs. CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench
    173 -- 187Sy-Yen Kuo, Kuochen Wang. Fault diagnosis in reconfigurable VLSI and WSI processor arrays

    Volume 2, Issue 2

    67 -- 0John A. Graniero, Claud N. Bain. Introduction
    79 -- 87M. J. Little, R. David Etchells, Jan Grinberg, S. P. Laub, J. G. Nash, M. W. Yung. The 3-D Computer
    89 -- 101M. J. Iacoponi. The Advanced Architecture On-board Processor signal processing testbed
    103 -- 109G. Melcher, G. Thomas, D. Kaplan. The Navy s new standard digital signal processor, the AN/UYS-2
    111 -- 116Earl E. Swartzlander Jr.. Generic signal processor implementation with VHSIC
    117 -- 121James B. Clary. Signal processing architecture assessment

    Volume 2, Issue 1

    5 -- 0Earl E. Swartzlander Jr.. Editorial
    7 -- 0Stuart Lawson, Steve Summerfield. The design of wave digital filters using fully pipelined bit-level systolic arrays
    9 -- 16Tom Kean, John Gray. Configurable hardware: Two case studies of micro-grain computation
    17 -- 27Luigi Dadda. A polyphase architecture for serial-input convolvers
    29 -- 36Paul S. Lewis. Systolic architectures for adaptive multichannel least squares lattice filters
    37 -- 49F. M. F. Gaston, George W. Irwin, J. G. McWhirter. Systolic square root covariance Kalman filtering
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