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Journal: VLSI Signal Processing
Home
Index
Info
Issue
Volume
2
, Issue
3
131
--
137
Graham A. Jullien
,
Subir Bandyopadhyay
,
William C. Miller
,
M. Taheri
.
A low-overhead scheme for testing a bit-level finite ring systolic array
139
--
148
Mark R. Greenstreet
,
Kenneth Steiglitz
.
Bubbles can make self-timed pipelines fast
149
--
158
M. Yan
,
John V. McCanny
.
A bit-level systolic architecture for implementing a VQ tree search
159
--
172
Thomas L. Wernimont
,
David K. Hwang
,
W. Kent Fuchs
.
CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench
173
--
187
Sy-Yen Kuo
,
Kuochen Wang
.
Fault diagnosis in reconfigurable VLSI and WSI processor arrays