External Links

    Journal: VLSI Signal Processing

    Volume 2, Issue 3

    131 -- 137Graham A. Jullien, Subir Bandyopadhyay, William C. Miller, M. Taheri. A low-overhead scheme for testing a bit-level finite ring systolic array
    139 -- 148Mark R. Greenstreet, Kenneth Steiglitz. Bubbles can make self-timed pipelines fast
    149 -- 158M. Yan, John V. McCanny. A bit-level systolic architecture for implementing a VQ tree search
    159 -- 172Thomas L. Wernimont, David K. Hwang, W. Kent Fuchs. CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench
    173 -- 187Sy-Yen Kuo, Kuochen Wang. Fault diagnosis in reconfigurable VLSI and WSI processor arrays
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