1 | -- | 2 | Wayne Luk, Yvon Savaria, Oskar Mencer. Guest Editorial: 20 Years of ASAP |
3 | -- | 14 | Earl E. Swartzlander Jr.. Systolic FFT Processors: A Personal Perspective |
15 | -- | 34 | Kung Yao, Flavio Lorenzelli. Systolic Algorithms and Architectures for High-Throughput Processing Applications |
35 | -- | 49 | Roger F. Woods, John V. McCanny, John G. McWhirter. From Bit Level Systolic Arrays to HDTV Processor Chips |
51 | -- | 71 | Florin Balasa, Per Gunnar Kjeldsberg, Arnout Vandecappelle, Martin Palkovic, Qubo Hu, Hongwei Zhu, Francky Catthoor. Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications |
73 | -- | 88 | Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro. Configurable LDPC Decoder Architectures for Regular and Irregular Codes |
89 | -- | 102 | Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede. Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class |
103 | -- | 112 | Francisco J. Jaime, Julio Villalba, Javier Hormigo, Emilio L. Zapata. Pipelined Architecture for Additive Range Reduction |
113 | -- | 127 | Grant Martin. Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors |
129 | -- | 143 | B. Neumann, Thorsten von Sydow, Holger Blume, Tobias G. Noll. Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs |
145 | -- | 169 | Yedidya Hilewitz, Ruby B. Lee. Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors |
171 | -- | 186 | Richard Hughey, Andrea Di Blas. Finding the Next Computational Model: Experience with the UCSC Kestrel |
187 | -- | 196 | Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin. Design, Debug, Deploy: The Creation of Configurable Computing Applications |
197 | -- | 215 | Peter R. Cappello. Application-specific Processor Architecture: Then and Now |
217 | -- | 229 | Yen-Kuang Chen, S. Y. Kung. Trend and Challenge on System-on-a-Chip Designs |