| 169 | -- | 171 | J. Takala, W. J. Gross, W. Sung. Guest Editors' Introduction to Special Issue on Advances in DSP System Design |
| 173 | -- | 187 | Wei-Chih Lai, Ching-Te Chiu. Data Center Switch for Load Balanced Fat-Trees |
| 189 | -- | 200 | Dong-hwan Lee, Wonyong Sung. Least Squares Based Coupling Cancelation for MLC NAND Flash Memory with a Small Number of Voltage Sensing Operations |
| 201 | -- | 219 | Mohammad M. Mansour. A Fast Recursive Algorithm and Architecture for Pruned Bit-reversal Interleavers |
| 221 | -- | 235 | Ricardo M. Sanchez, Paul A. RodrĂguez. Highly Parallelable Bidimensional Median Filter for Modern Parallel Programming Models |
| 237 | -- | 246 | Yun Pan, Ning Zheng, Qinglin Tian, Xiaolang Yan, Ruohong Huan. Hierarchical Resampling Algorithm and Architecture for Distributed Particle Filters |
| 247 | -- | 260 | Chi Ching Chi, Mauricio Alvarez Mesa, Jan Lucas, Ben H. H. Juurlink, Thomas Schierl. Parallel HEVC Decoding on Multi- and Many-core Architectures - A Power and Performance Analysis |
| 261 | -- | 273 | Jiayi Du, Yan Wang, Qingfeng Zhuge, Jingtong Hu, Edwin Hsing-Mean Sha. Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory |
| 275 | -- | 286 | Lai-Huei Wang, Chung-Ching Shen, Shenpei Wu, Shuvra S. Bhattacharyya. Parameterized Scheduling of Topological Patterns in Signal Processing Dataflow Graphs |
| 287 | -- | 296 | Helena Leppäkoski, Jussi Collin, Jarmo Takala. Pedestrian Navigation Based on Inertial Sensors, Indoor Map, and WLAN Signals |
| 297 | -- | 312 | Qiuling Zhu, Christian R. Berger, Eric L. Turner, Larry Pileggi, Franz Franchetti. Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation |