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    Journal: VLSI Signal Processing

    Volume 71, Issue 3

    169 -- 171J. Takala, W. J. Gross, W. Sung. Guest Editors' Introduction to Special Issue on Advances in DSP System Design
    173 -- 187Wei-Chih Lai, Ching-Te Chiu. Data Center Switch for Load Balanced Fat-Trees
    189 -- 200Dong-hwan Lee, Wonyong Sung. Least Squares Based Coupling Cancelation for MLC NAND Flash Memory with a Small Number of Voltage Sensing Operations
    201 -- 219Mohammad M. Mansour. A Fast Recursive Algorithm and Architecture for Pruned Bit-reversal Interleavers
    221 -- 235Ricardo M. Sanchez, Paul A. Rodríguez. Highly Parallelable Bidimensional Median Filter for Modern Parallel Programming Models
    237 -- 246Yun Pan, Ning Zheng, Qinglin Tian, Xiaolang Yan, Ruohong Huan. Hierarchical Resampling Algorithm and Architecture for Distributed Particle Filters
    247 -- 260Chi Ching Chi, Mauricio Alvarez Mesa, Jan Lucas, Ben H. H. Juurlink, Thomas Schierl. Parallel HEVC Decoding on Multi- and Many-core Architectures - A Power and Performance Analysis
    261 -- 273Jiayi Du, Yan Wang, Qingfeng Zhuge, Jingtong Hu, Edwin Hsing-Mean Sha. Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory
    275 -- 286Lai-Huei Wang, Chung-Ching Shen, Shenpei Wu, Shuvra S. Bhattacharyya. Parameterized Scheduling of Topological Patterns in Signal Processing Dataflow Graphs
    287 -- 296Helena Leppäkoski, Jussi Collin, Jarmo Takala. Pedestrian Navigation Based on Inertial Sensors, Indoor Map, and WLAN Signals
    297 -- 312Qiuling Zhu, Christian R. Berger, Eric L. Turner, Larry Pileggi, Franz Franchetti. Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation

    Volume 71, Issue 2

    89 -- 103Rafael Ramos-Lara, Mariano Lopez Garcia, Enrique F. Cantó-Navarro, Luis Puente-Rodriguez. Real-Time Speaker Verification System Implemented on Reconfigurable Hardware
    105 -- 109Pedro Echeverría, Marisa López-Vallejo. High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator
    111 -- 121Mohammad Reza Hosseiny Fatemi, Hasan F. Ates, Rosli Salleh. Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVC
    123 -- 142Ishmael Sameen, Yoong Choon Chang, Mow Song Ng, Bok-Min Goi, Chee-Pun Ooi. A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform
    143 -- 157Jingtong Hu, Chun Jason Xue, Meikang Qiu, Wei-Che Tseng, Edwin Hsing-Mean Sha. Algorithms to Minimize Data Transfer for Code Update on Wireless Sensor Network
    159 -- 168Jaehyun Baek, Myung Hoon Sunwoo. New Cost-Effective Simplified Euclid's Algorithm for Reed-Solomon Decoders

    Volume 71, Issue 1

    1 -- 20Alexandre Borghi, Jérôme Darbon, Sylvain Peyronnet, Tony F. Chan, Stanley Osher. A Simple Compressive Sensing Algorithm for Parallel Many-Core Architectures
    21 -- 34Shiyan Wang, Huimin Yu, Roland Hu. 3D Video Based Segmentation and Motion Estimation with Active Surface Evolution
    35 -- 40Jani Boutellier, Mickaël Raulet, Olli Silvén. Automatic Hierarchical Discovery of Quasi-Static Schedules of RVC-CAL Dataflow Programs
    41 -- 55Milad Ghantous, Magdy Bayoumi. MIRF: A Multimodal Image Registration and Fusion Module Based on DT-CWT
    57 -- 73Marek Wojcikowski, Robert Zaglewski, Bogdan Pankiewicz, Miron Klosowski, Stanislaw Szczepanski. Hardware-Software Implementation of a Sensor Network for City Traffic Monitoring Using the FPGA- and ASIC-Based Sensor Nodes
    75 -- 88Hyunok Oh. Port Based Actor Model with Kahn Process Network Model and Decidable Dataflow Model
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