Journal: VLSI Signal Processing

Volume 24, Issue 2-3

127 -- 0Jeffrey Arnold, Wayne Luk, Ken Pocek. Guest Editors Introduction
129 -- 146Herman Schmit, Srihari Cadambi, Matthew Moe, Seth Copen Goldstein. Pipeline Reconfigurable FPGAs
147 -- 164Ming-Hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves. Design and Implementation of the MorphoSys Reconfigurable Computing Processor
165 -- 180Maya Gokhale, Janice M. Stone, Edson Gomersall. Co-Synthesis to a Hybrid RISC/FPGA Architecture
181 -- 209Meenakshi Kaul, Ranga Vemuri. Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems
211 -- 221Oskar Mencer, Luc Séméria, Martin Morf, Jean-Marc Delosme. Application of Reconfigurable CORDIC Architectures
223 -- 240Panagiotis Stogiannos, Apostolos Dollas, Vassilios Digalakis. A Configurable Logic Based Architecture for Real-Time Continuous Speech Recognition Using Hidden Markov Models
241 -- 262Hugo de Garis, Michael Korkin. The CAM-Brain Machine (CBM): Real Time Evolution and Update of a 75 Million Neuron FPGA-Based Artificial Brain

Volume 24, Issue 1

5 -- 6Elias S. Manolakos, Wayne Burleson. Guest Editor s Introduction
9 -- 18Paul D. Fiore. Efficient Wordlength Reduction Techniques for DSP Applications
19 -- 30Shiro Kobayashi, Gerhard Fettweis. A Hierarchical Block-Floating-Point Arithmetic
31 -- 41Richard P. Kleihorst, René J. van der Vleuten. DCT-Domain Embedded Memory Compression for Hybrid Video Coders
43 -- 57Sangjin Hong, Wayne E. Stark. Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications
59 -- 65Sydney Reader, Won Namgoong, Teresa H. Y. Meng. Partitioning Analog and Digital Processing in Mixed-Signal Systems
67 -- 81Gaye Lightbody, Richard Walke, Roger Woods, John V. McCanny. Linear QR Architecture for a Single Chip Adaptive Beamformer
83 -- 98Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya. Multidimensional Exploration of Software Implementations for DSP Algorithms
99 -- 120Andrew Stone, Elias S. Manolakos. DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures