Journal: VLSI Signal Processing

Volume 6, Issue 3

7 -- 0Miriam Leeser. High level synthesis and generation FPGAs with the BEDROC system
219 -- 231Giulio Casagrande, Armando Chiari, Carla Golla, Salvatore Miceli. Vlsi programmable digital filter for video signal processing
233 -- 242David M. Mandelbaum. A method for calculation of the square root using combinatorial logic
243 -- 257Tom Chen, Li Zhu. An expandable column fft architecture using circuit switching networks
259 -- 269Jenn-Dong Sun, Hari Krishna, K.-Y. Lin. A superfast algorithm for single-error correction in rrns and hardware implementation
271 -- 288Shuvra S. Bhattacharyya, Edward A. Lee. Scheduling synchronous dataflow graphs for efficient looping
289 -- 299Jos Huisken, A. Delaruelle, B. Egberts, P. Eeckhout, Jef L. van Meerbergen. Synthesis of synchronous communication hardware in a multiprocessor architecture

Volume 6, Issue 2

99 -- 100Will Moore, Wayne Luk. Introduction
101 -- 117Gordon J. Brebner. Configurable array logic circuits for computing network error detection codes
129 -- 137Barry S. Fagin. Quantitative measurements of FPGA utility in special and general purpose processors
139 -- 153Sean Monaghan. A gate-level reconfigurable Monte carlo processor
155 -- 172Jouni Isoaho, Jari Pasanen, Olli Vainio, Hannu Tenhunen. DSP system integration and prototyping with FPGAS
173 -- 190Erik Brunvand. Using FPGAs to implement self-timed systems
191 -- 214Miriam Leeser, Richard Chapman, Mark Aagaard, Mark H. Linderman, Stephan Meier. High level synthesis and generating FPGAs with the BEDROC system

Volume 6, Issue 1

5 -- 0Hans Peter Graf. Special issue on VLSI neural networks
7 -- 18Yuzo Hirai. Recent VLSI neural networks in Japan
19 -- 31Hans Peter Graf, Eduard Säckinger, Lawrence D. Jackel. Recent developments of electronic neural nets in North America
33 -- 44Krste Asanovic, Nelson Morgan, John Wawrzynek. Using simulations of reduced precision arithmetic to design a neuro-microprocessor
45 -- 56Ulrich Ramacher, Jörg Beichter, Nico Brüls. A general-purpose signal processor architecture for neurocomputing and preprocessing applications
57 -- 66Ji-chien Lee, Bing J. Sheu, Rama Chellappa. A mixed-signal VLSI competitive neuroprocessor for video motion detection
67 -- 76Marwan A. Jabri, Stephen Pickard, P. Leong, Y. Xie. Algorithmic and implementation issues in analog low power learning neural network chips
77 -- 84Yu-jhih Wu, Michael D. Alston, Paul M. Chau. Dynamic adaptation of quantization thresholds for soft-decision viterbi decoding with a reinforcement learning neural network
85 -- 94Karl-Heinz Zimmermann, Tien-Chien Lee, Sun-Yuan Kung. On partitioning and fault tolerance issues for neural array processors